Single Chip Programmable Baseband ASSP for 5 GHz Wireless LAN Applications

Johannes KNEIP; Matthias WEISS; Wolfram DRESCHER; Volker AUE; Jurgen STROBEL; Thomas OBERTHUR; Michael BOLLE; Gerhard FETTWEIS

Single Chip Programmable Baseband ASSP for 5 GHz Wireless LAN Applications

Johannes KNEIP, Matthias WEISS, Wolfram DRESCHER, Volker AUE, Jurgen STROBEL, Thomas OBERTHUR, Michael BOLLE, Gerhard FETTWEIS

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This paper presents the HiperSonic 1, a multi-standard, application-specific signal processor, designed to execute the baseband conversion algorithms in IEEE802.11a- and HIPERLAN/2-based 5 GHz wireless LAN applications. In contrast to widely existing, dedicated implementations, most of the computational effort here was mapped onto a configurable, data- and instruction-parallel DSP core. The core is supplemented by mixed signal A/D, D/A converters and hardware accelerators. Memory and register architecture, instruction set and peripheral interfaces of the chip were carefully optimized for the targeted applications, leading to a sound combination of flexibility, die area and power consumption. The 120 MHz, 7.6 million-transistor solution was implemented in 0.18 µm CMOS and performs IEEE802.11a or HiperLAN/2 compliant baseband processing at data rates up to 60 Mbit/s.

Publication: IEICE TRANSACTIONS on Electronics Vol.E85-C No.2 pp.359-367

Publication Date: 2002/02/01

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Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)

Category: Product Designs

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Johannes KNEIP, Matthias WEISS, Wolfram DRESCHER, Volker AUE, Jurgen STROBEL, Thomas OBERTHUR, Michael BOLLE, Gerhard FETTWEIS, "Single Chip Programmable Baseband ASSP for 5 GHz Wireless LAN Applications" in IEICE TRANSACTIONS on Electronics, vol. E85-C, no. 2, pp. 359-367, February 2002, doi: .
Abstract: This paper presents the HiperSonic 1, a multi-standard, application-specific signal processor, designed to execute the baseband conversion algorithms in IEEE802.11a- and HIPERLAN/2-based 5 GHz wireless LAN applications. In contrast to widely existing, dedicated implementations, most of the computational effort here was mapped onto a configurable, data- and instruction-parallel DSP core. The core is supplemented by mixed signal A/D, D/A converters and hardware accelerators. Memory and register architecture, instruction set and peripheral interfaces of the chip were carefully optimized for the targeted applications, leading to a sound combination of flexibility, die area and power consumption. The 120 MHz, 7.6 million-transistor solution was implemented in 0.18 µm CMOS and performs IEEE802.11a or HiperLAN/2 compliant baseband processing at data rates up to 60 Mbit/s.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_359/_p

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@ARTICLE{e85-c_2_359,
author={Johannes KNEIP, Matthias WEISS, Wolfram DRESCHER, Volker AUE, Jurgen STROBEL, Thomas OBERTHUR, Michael BOLLE, Gerhard FETTWEIS, },
journal={IEICE TRANSACTIONS on Electronics},
title={Single Chip Programmable Baseband ASSP for 5 GHz Wireless LAN Applications},
year={2002},
volume={E85-C},
number={2},
pages={359-367},
abstract={This paper presents the HiperSonic 1, a multi-standard, application-specific signal processor, designed to execute the baseband conversion algorithms in IEEE802.11a- and HIPERLAN/2-based 5 GHz wireless LAN applications. In contrast to widely existing, dedicated implementations, most of the computational effort here was mapped onto a configurable, data- and instruction-parallel DSP core. The core is supplemented by mixed signal A/D, D/A converters and hardware accelerators. Memory and register architecture, instruction set and peripheral interfaces of the chip were carefully optimized for the targeted applications, leading to a sound combination of flexibility, die area and power consumption. The 120 MHz, 7.6 million-transistor solution was implemented in 0.18 µm CMOS and performs IEEE802.11a or HiperLAN/2 compliant baseband processing at data rates up to 60 Mbit/s.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - Single Chip Programmable Baseband ASSP for 5 GHz Wireless LAN Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 359
EP - 367
AU - Johannes KNEIP
AU - Matthias WEISS
AU - Wolfram DRESCHER
AU - Volker AUE
AU - Jurgen STROBEL
AU - Thomas OBERTHUR
AU - Michael BOLLE
AU - Gerhard FETTWEIS
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - This paper presents the HiperSonic 1, a multi-standard, application-specific signal processor, designed to execute the baseband conversion algorithms in IEEE802.11a- and HIPERLAN/2-based 5 GHz wireless LAN applications. In contrast to widely existing, dedicated implementations, most of the computational effort here was mapped onto a configurable, data- and instruction-parallel DSP core. The core is supplemented by mixed signal A/D, D/A converters and hardware accelerators. Memory and register architecture, instruction set and peripheral interfaces of the chip were carefully optimized for the targeted applications, leading to a sound combination of flexibility, die area and power consumption. The 120 MHz, 7.6 million-transistor solution was implemented in 0.18 µm CMOS and performs IEEE802.11a or HiperLAN/2 compliant baseband processing at data rates up to 60 Mbit/s.
ER -