Design of a 44 Banyan Network Switch with a Dual-Buffer Structure Using SFQ Logic Circuits

Junji TAKAHASHI, Hiroaki MYOREN, Susumu TAKADA

Summary :

We have designed a 44 Banyan switch using SFQ logic circuits. The switch is composed of three parts; one is an input buffer, the second is a contention solver which checks packet contention in a distribution network, and the third is a packet distribution network which distributes contention-free packets to their destination address. The packet distribution network is composed of Batcher-Banyan switch with the input buffer. The contention solver decides to send a data packet to the distribution network, using only internal routing tags which are added to packets in the switch. As the circuit is composed of two parts, the contention solver and the packet distribution network, the transfer rate is raised because it doesn't need to wait any more while a data packet passes through the distribution network. Simulation results using JSIM show that the switch circuit can operate at a clock frequency of 40 GHz.

• Publication: IEICE TRANSACTIONS on Electronics Vol.E86-C No.1 pp.9-15
• Publication Date: 2003/01/01
• Type of Manuscript: Special Section PAPER (Special Issue on Superconductor Digital/Analog Circuit Technologies)
• Category: LTS Digital Application

Authors

Junji TAKAHASHI
Hiroaki MYOREN
Susumu TAKADA

Keyword

SFQ logic,  Banyan switch,  packet,  internal routing tag