IEICE TRANSACTIONS on Electronics
Gate Array Using Low-Temperature Poly-Si Thin-Film Transistors
Summary :
We have designed gate arrays using low-temperature poly-Si thin-film transistors and confirmed the correct operations. Various kinds of logic gates are beforehand prepared, contact holes are later bored, and mutual wiring is formed between the logic gates on demand. A half adder, two-bit decoder, and flip flop are composed as examples. The static behaviors are evaluated, and it is confirmed that the correct waveforms are output. The dynamic behaviors are also evaluated, and it is concluded that the dynamic behaviors of the gate array are less deteriorated than that of the independent circuit.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E103-C No.7 pp.341-344
- Publication Date
- 2020/07/01
- Publicized
- 2020/01/27
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2018ECP5067
- Type of Manuscript
- PAPER
- Category
- Semiconductor Materials and Devices
Authors
Mutsumi KIMURA
Ryukoku University,High-Tech Research Center
Masashi INOUE
Ryukoku University
Tokiyoshi MATSUDA
High-Tech Research Center
Keyword
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Mutsumi KIMURA, Masashi INOUE, Tokiyoshi MATSUDA, "Gate Array Using Low-Temperature Poly-Si Thin-Film Transistors" in IEICE TRANSACTIONS on Electronics,
vol. E103-C, no. 7, pp. 341-344, July 2020, doi: 10.1587/transele.2018ECP5067.
Abstract: We have designed gate arrays using low-temperature poly-Si thin-film transistors and confirmed the correct operations. Various kinds of logic gates are beforehand prepared, contact holes are later bored, and mutual wiring is formed between the logic gates on demand. A half adder, two-bit decoder, and flip flop are composed as examples. The static behaviors are evaluated, and it is confirmed that the correct waveforms are output. The dynamic behaviors are also evaluated, and it is concluded that the dynamic behaviors of the gate array are less deteriorated than that of the independent circuit.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2018ECP5067/_p
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@ARTICLE{e103-c_7_341,
author={Mutsumi KIMURA, Masashi INOUE, Tokiyoshi MATSUDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Gate Array Using Low-Temperature Poly-Si Thin-Film Transistors},
year={2020},
volume={E103-C},
number={7},
pages={341-344},
abstract={We have designed gate arrays using low-temperature poly-Si thin-film transistors and confirmed the correct operations. Various kinds of logic gates are beforehand prepared, contact holes are later bored, and mutual wiring is formed between the logic gates on demand. A half adder, two-bit decoder, and flip flop are composed as examples. The static behaviors are evaluated, and it is confirmed that the correct waveforms are output. The dynamic behaviors are also evaluated, and it is concluded that the dynamic behaviors of the gate array are less deteriorated than that of the independent circuit.},
keywords={},
doi={10.1587/transele.2018ECP5067},
ISSN={1745-1353},
month={July},}
Copy
TY - JOUR
TI - Gate Array Using Low-Temperature Poly-Si Thin-Film Transistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 341
EP - 344
AU - Mutsumi KIMURA
AU - Masashi INOUE
AU - Tokiyoshi MATSUDA
PY - 2020
DO - 10.1587/transele.2018ECP5067
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E103-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2020
AB - We have designed gate arrays using low-temperature poly-Si thin-film transistors and confirmed the correct operations. Various kinds of logic gates are beforehand prepared, contact holes are later bored, and mutual wiring is formed between the logic gates on demand. A half adder, two-bit decoder, and flip flop are composed as examples. The static behaviors are evaluated, and it is confirmed that the correct waveforms are output. The dynamic behaviors are also evaluated, and it is concluded that the dynamic behaviors of the gate array are less deteriorated than that of the independent circuit.
ER -
English
