A Micro-Code-Based IME Engine for HEVC and Its Hardware Implementation

Leilei HUANG; Yibo FAN; Chenhao GU; Xiaoyang ZENG

doi:10.1587/transele.2018ECP5077

A Micro-Code-Based IME Engine for HEVC and Its Hardware Implementation

Leilei HUANG, Yibo FAN, Chenhao GU, Xiaoyang ZENG

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High Efficiency Video Coding (HEVC) standard is now becoming one of the most widespread video coding standards in the world. As a successor of H.264 standard, it aims to provide a much superior encoding performance. To fulfill this goal, several new notations along with the corresponding computation processes are introduced by this standard. Among those computation processes, the integer motion estimation (IME) is one of bottlenecks due to the complex partitions of the inter prediction units (PU) and the large search window commonly adopted. Many algorithms have been proposed to address this issue and usually put emphasis on a large search window and great computation amount. However, the coding efforts should be related to the scenes. To be more specific, for relatively static videos, a small search window along with a simple search scheme should be adopted to reduce the time cost and power consumption. In view of this, a micro-code-based IME engine is proposed in this paper, which could be applied with search schemes of different complexity. To test the performance, three different search schemes based on this engine are designed and evaluated under HEVC test model (HM) 16.9, achieving a B-D rate increase of 0.55/-0.07/-0.14%. Compared with our previous work, the hardware implementation is optimized to reduce 64.2% of the SRAMs bits and 32.8% of the logic gate count. The final design could support 4K×2K @139/85/37fps videos @500MHz.

Publication: IEICE TRANSACTIONS on Electronics Vol.E102-C No.10 pp.756-765

Publication Date: 2019/10/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.2018ECP5077

Type of Manuscript: PAPER

Category: Integrated Electronics

Authors

Leilei HUANG
  Fudan University
Yibo FAN
  Fudan University
Chenhao GU
  Fudan University
Xiaoyang ZENG
  Fudan University

Keyword

high efficiency video coding (HEVC), integer motion estimation (IME), hardware implementation, very large scale integration (VLSI)

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Leilei HUANG, Yibo FAN, Chenhao GU, Xiaoyang ZENG, "A Micro-Code-Based IME Engine for HEVC and Its Hardware Implementation" in IEICE TRANSACTIONS on Electronics, vol. E102-C, no. 10, pp. 756-765, October 2019, doi: 10.1587/transele.2018ECP5077.
Abstract: High Efficiency Video Coding (HEVC) standard is now becoming one of the most widespread video coding standards in the world. As a successor of H.264 standard, it aims to provide a much superior encoding performance. To fulfill this goal, several new notations along with the corresponding computation processes are introduced by this standard. Among those computation processes, the integer motion estimation (IME) is one of bottlenecks due to the complex partitions of the inter prediction units (PU) and the large search window commonly adopted. Many algorithms have been proposed to address this issue and usually put emphasis on a large search window and great computation amount. However, the coding efforts should be related to the scenes. To be more specific, for relatively static videos, a small search window along with a simple search scheme should be adopted to reduce the time cost and power consumption. In view of this, a micro-code-based IME engine is proposed in this paper, which could be applied with search schemes of different complexity. To test the performance, three different search schemes based on this engine are designed and evaluated under HEVC test model (HM) 16.9, achieving a B-D rate increase of 0.55/-0.07/-0.14%. Compared with our previous work, the hardware implementation is optimized to reduce 64.2% of the SRAMs bits and 32.8% of the logic gate count. The final design could support 4K×2K @139/85/37fps videos @500MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2018ECP5077/_p

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@ARTICLE{e102-c_10_756,
author={Leilei HUANG, Yibo FAN, Chenhao GU, Xiaoyang ZENG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Micro-Code-Based IME Engine for HEVC and Its Hardware Implementation},
year={2019},
volume={E102-C},
number={10},
pages={756-765},
abstract={High Efficiency Video Coding (HEVC) standard is now becoming one of the most widespread video coding standards in the world. As a successor of H.264 standard, it aims to provide a much superior encoding performance. To fulfill this goal, several new notations along with the corresponding computation processes are introduced by this standard. Among those computation processes, the integer motion estimation (IME) is one of bottlenecks due to the complex partitions of the inter prediction units (PU) and the large search window commonly adopted. Many algorithms have been proposed to address this issue and usually put emphasis on a large search window and great computation amount. However, the coding efforts should be related to the scenes. To be more specific, for relatively static videos, a small search window along with a simple search scheme should be adopted to reduce the time cost and power consumption. In view of this, a micro-code-based IME engine is proposed in this paper, which could be applied with search schemes of different complexity. To test the performance, three different search schemes based on this engine are designed and evaluated under HEVC test model (HM) 16.9, achieving a B-D rate increase of 0.55/-0.07/-0.14%. Compared with our previous work, the hardware implementation is optimized to reduce 64.2% of the SRAMs bits and 32.8% of the logic gate count. The final design could support 4K×2K @139/85/37fps videos @500MHz.},
keywords={},
doi={10.1587/transele.2018ECP5077},
ISSN={1745-1353},
month={October},}

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TY - JOUR
TI - A Micro-Code-Based IME Engine for HEVC and Its Hardware Implementation
T2 - IEICE TRANSACTIONS on Electronics
SP - 756
EP - 765
AU - Leilei HUANG
AU - Yibo FAN
AU - Chenhao GU
AU - Xiaoyang ZENG
PY - 2019
DO - 10.1587/transele.2018ECP5077
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2019
AB - High Efficiency Video Coding (HEVC) standard is now becoming one of the most widespread video coding standards in the world. As a successor of H.264 standard, it aims to provide a much superior encoding performance. To fulfill this goal, several new notations along with the corresponding computation processes are introduced by this standard. Among those computation processes, the integer motion estimation (IME) is one of bottlenecks due to the complex partitions of the inter prediction units (PU) and the large search window commonly adopted. Many algorithms have been proposed to address this issue and usually put emphasis on a large search window and great computation amount. However, the coding efforts should be related to the scenes. To be more specific, for relatively static videos, a small search window along with a simple search scheme should be adopted to reduce the time cost and power consumption. In view of this, a micro-code-based IME engine is proposed in this paper, which could be applied with search schemes of different complexity. To test the performance, three different search schemes based on this engine are designed and evaluated under HEVC test model (HM) 16.9, achieving a B-D rate increase of 0.55/-0.07/-0.14%. Compared with our previous work, the hardware implementation is optimized to reduce 64.2% of the SRAMs bits and 32.8% of the logic gate count. The final design could support 4K×2K @139/85/37fps videos @500MHz.
ER -