IEICE TRANSACTIONS on Electronics
Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler
Summary :
Utilization of local memory from real-time embedded systems to high performance systems with multi-core processors has become an important factor for satisfying hard deadline constraints. However, challenges lie in the area of efficiently managing the memory hierarchy, such as decomposing large data into small blocks to fit onto local memory and transferring blocks for reuse and replacement. To address this issue, this paper presents a compiler optimization method that automatically manage local memory of multi-core processors. The method selects and maps multi-dimensional data onto software specified memory blocks called Adjustable Blocks. These blocks are hierarchically divisible with varying sizes defined by the features of the input application. Moreover, the method introduces mapping structures called Template Arrays to maintain the indices of the decomposed multi-dimensional data. The proposed work is implemented on the OSCAR automatic parallelizing compiler and evaluations were performed on the Renesas RP2 8-core processor. Experimental results from NAS Parallel Benchmark, SPEC benchmark, and multimedia applications show the effectiveness of the method, obtaining maximum speed-ups of 20.44 with 8 cores utilizing local memory from single core sequential versions that use off-chip memory.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E103-C No.3 pp.98-109
- Publication Date
- 2020/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2019LHP0010
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
- Category
Authors
Yoshitake OKI
Waseda University
Yuto ABE
Waseda University
Kazuki YAMAMOTO
Waseda University
Kohei YAMAMOTO
Waseda University
Tomoya SHIRAKAWA
Waseda University
Akimasa YOSHIDA
Meiji University
Keiji KIMURA
Waseda University
Hironori KASAHARA
Waseda University
Keyword
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Yoshitake OKI, Yuto ABE, Kazuki YAMAMOTO, Kohei YAMAMOTO, Tomoya SHIRAKAWA, Akimasa YOSHIDA, Keiji KIMURA, Hironori KASAHARA, "Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler" in IEICE TRANSACTIONS on Electronics,
vol. E103-C, no. 3, pp. 98-109, March 2020, doi: 10.1587/transele.2019LHP0010.
Abstract: Utilization of local memory from real-time embedded systems to high performance systems with multi-core processors has become an important factor for satisfying hard deadline constraints. However, challenges lie in the area of efficiently managing the memory hierarchy, such as decomposing large data into small blocks to fit onto local memory and transferring blocks for reuse and replacement. To address this issue, this paper presents a compiler optimization method that automatically manage local memory of multi-core processors. The method selects and maps multi-dimensional data onto software specified memory blocks called Adjustable Blocks. These blocks are hierarchically divisible with varying sizes defined by the features of the input application. Moreover, the method introduces mapping structures called Template Arrays to maintain the indices of the decomposed multi-dimensional data. The proposed work is implemented on the OSCAR automatic parallelizing compiler and evaluations were performed on the Renesas RP2 8-core processor. Experimental results from NAS Parallel Benchmark, SPEC benchmark, and multimedia applications show the effectiveness of the method, obtaining maximum speed-ups of 20.44 with 8 cores utilizing local memory from single core sequential versions that use off-chip memory.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019LHP0010/_p
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@ARTICLE{e103-c_3_98,
author={Yoshitake OKI, Yuto ABE, Kazuki YAMAMOTO, Kohei YAMAMOTO, Tomoya SHIRAKAWA, Akimasa YOSHIDA, Keiji KIMURA, Hironori KASAHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler},
year={2020},
volume={E103-C},
number={3},
pages={98-109},
abstract={Utilization of local memory from real-time embedded systems to high performance systems with multi-core processors has become an important factor for satisfying hard deadline constraints. However, challenges lie in the area of efficiently managing the memory hierarchy, such as decomposing large data into small blocks to fit onto local memory and transferring blocks for reuse and replacement. To address this issue, this paper presents a compiler optimization method that automatically manage local memory of multi-core processors. The method selects and maps multi-dimensional data onto software specified memory blocks called Adjustable Blocks. These blocks are hierarchically divisible with varying sizes defined by the features of the input application. Moreover, the method introduces mapping structures called Template Arrays to maintain the indices of the decomposed multi-dimensional data. The proposed work is implemented on the OSCAR automatic parallelizing compiler and evaluations were performed on the Renesas RP2 8-core processor. Experimental results from NAS Parallel Benchmark, SPEC benchmark, and multimedia applications show the effectiveness of the method, obtaining maximum speed-ups of 20.44 with 8 cores utilizing local memory from single core sequential versions that use off-chip memory.},
keywords={},
doi={10.1587/transele.2019LHP0010},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler
T2 - IEICE TRANSACTIONS on Electronics
SP - 98
EP - 109
AU - Yoshitake OKI
AU - Yuto ABE
AU - Kazuki YAMAMOTO
AU - Kohei YAMAMOTO
AU - Tomoya SHIRAKAWA
AU - Akimasa YOSHIDA
AU - Keiji KIMURA
AU - Hironori KASAHARA
PY - 2020
DO - 10.1587/transele.2019LHP0010
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E103-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2020
AB - Utilization of local memory from real-time embedded systems to high performance systems with multi-core processors has become an important factor for satisfying hard deadline constraints. However, challenges lie in the area of efficiently managing the memory hierarchy, such as decomposing large data into small blocks to fit onto local memory and transferring blocks for reuse and replacement. To address this issue, this paper presents a compiler optimization method that automatically manage local memory of multi-core processors. The method selects and maps multi-dimensional data onto software specified memory blocks called Adjustable Blocks. These blocks are hierarchically divisible with varying sizes defined by the features of the input application. Moreover, the method introduces mapping structures called Template Arrays to maintain the indices of the decomposed multi-dimensional data. The proposed work is implemented on the OSCAR automatic parallelizing compiler and evaluations were performed on the Renesas RP2 8-core processor. Experimental results from NAS Parallel Benchmark, SPEC benchmark, and multimedia applications show the effectiveness of the method, obtaining maximum speed-ups of 20.44 with 8 cores utilizing local memory from single core sequential versions that use off-chip memory.
ER -
English
