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Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism

Yuta UKON, Shimpei SATO, Atsushi TAKAHASHI

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Summary :

Advanced information-processing services such as computer vision require a high-performance digital circuit to perform high-load processing at high speed. To achieve high-speed processing, several image-processing applications use an approximate computing technique to reduce idle time of the circuit. However, it is difficult to design the high-speed image-processing circuit while controlling the error rate so as not to degrade service quality, and this technique is used for only a few applications. In this paper, we propose a method that achieves high-speed processing effectively in which processing time for each task is changed by roughly detecting its completion. Using this method, a high-speed processing circuit with a low error rate can be designed. The error rate is controllable, and a circuit design method to minimize the error rate is also presented in this paper. To confirm the effectiveness of our proposal, a ripple-carry adder (RCA), 2-dimensional discrete cosine transform (2D-DCT) circuit, and histogram of oriented gradients (HOG) feature calculation circuit are evaluated. Effective clock periods of these circuits obtained by our method with around 1% error rate are improved about 64%, 6%, and 12%, respectively, compared with circuits without error. Furthermore, the impact of the miscalculation on a video monitoring service using an object detection application is investigated. As a result, more than 99% of detection points required to be obtained are detected, and it is confirmed the miscalculation hardly degrades the service quality.

Publication
IEICE TRANSACTIONS on Electronics Vol.E104-C No.7 pp.309-318
Publication Date
2021/07/01
Publicized
2020/12/21
Online ISSN
1745-1353
DOI
10.1587/transele.2020CDP0007
Type of Manuscript
Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category

Authors

Yuta UKON
  Tokyo Institute of Technology
Shimpei SATO
  Tokyo Institute of Technology
Atsushi TAKAHASHI
  Tokyo Institute of Technology

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