Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism

Yuta UKON; Shimpei SATO; Atsushi TAKAHASHI

doi:10.1587/transele.2020CDP0007

IEICE TRANSACTIONS on Electronics

Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism

Yuta UKON, Shimpei SATO, Atsushi TAKAHASHI

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Advanced information-processing services such as computer vision require a high-performance digital circuit to perform high-load processing at high speed. To achieve high-speed processing, several image-processing applications use an approximate computing technique to reduce idle time of the circuit. However, it is difficult to design the high-speed image-processing circuit while controlling the error rate so as not to degrade service quality, and this technique is used for only a few applications. In this paper, we propose a method that achieves high-speed processing effectively in which processing time for each task is changed by roughly detecting its completion. Using this method, a high-speed processing circuit with a low error rate can be designed. The error rate is controllable, and a circuit design method to minimize the error rate is also presented in this paper. To confirm the effectiveness of our proposal, a ripple-carry adder (RCA), 2-dimensional discrete cosine transform (2D-DCT) circuit, and histogram of oriented gradients (HOG) feature calculation circuit are evaluated. Effective clock periods of these circuits obtained by our method with around 1% error rate are improved about 64%, 6%, and 12%, respectively, compared with circuits without error. Furthermore, the impact of the miscalculation on a video monitoring service using an object detection application is investigated. As a result, more than 99% of detection points required to be obtained are detected, and it is confirmed the miscalculation hardly degrades the service quality.

Publication: IEICE TRANSACTIONS on Electronics Vol.E104-C No.7 pp.309-318

Publication Date: 2021/07/01

Publicized: 2020/12/21

Online ISSN: 1745-1353

DOI: 10.1587/transele.2020CDP0007

Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)

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Authors

Yuta UKON
  Tokyo Institute of Technology
Shimpei SATO
  Tokyo Institute of Technology
Atsushi TAKAHASHI
  Tokyo Institute of Technology

Keyword

digital circuit design, variable-latency circuit, signal monitoring, approximate completion-detection mechanism

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Yuta UKON, Shimpei SATO, Atsushi TAKAHASHI, "Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism" in IEICE TRANSACTIONS on Electronics, vol. E104-C, no. 7, pp. 309-318, July 2021, doi: 10.1587/transele.2020CDP0007.
Abstract: Advanced information-processing services such as computer vision require a high-performance digital circuit to perform high-load processing at high speed. To achieve high-speed processing, several image-processing applications use an approximate computing technique to reduce idle time of the circuit. However, it is difficult to design the high-speed image-processing circuit while controlling the error rate so as not to degrade service quality, and this technique is used for only a few applications. In this paper, we propose a method that achieves high-speed processing effectively in which processing time for each task is changed by roughly detecting its completion. Using this method, a high-speed processing circuit with a low error rate can be designed. The error rate is controllable, and a circuit design method to minimize the error rate is also presented in this paper. To confirm the effectiveness of our proposal, a ripple-carry adder (RCA), 2-dimensional discrete cosine transform (2D-DCT) circuit, and histogram of oriented gradients (HOG) feature calculation circuit are evaluated. Effective clock periods of these circuits obtained by our method with around 1% error rate are improved about 64%, 6%, and 12%, respectively, compared with circuits without error. Furthermore, the impact of the miscalculation on a video monitoring service using an object detection application is investigated. As a result, more than 99% of detection points required to be obtained are detected, and it is confirmed the miscalculation hardly degrades the service quality.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2020CDP0007/_p

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@ARTICLE{e104-c_7_309,
author={Yuta UKON, Shimpei SATO, Atsushi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism},
year={2021},
volume={E104-C},
number={7},
pages={309-318},
abstract={Advanced information-processing services such as computer vision require a high-performance digital circuit to perform high-load processing at high speed. To achieve high-speed processing, several image-processing applications use an approximate computing technique to reduce idle time of the circuit. However, it is difficult to design the high-speed image-processing circuit while controlling the error rate so as not to degrade service quality, and this technique is used for only a few applications. In this paper, we propose a method that achieves high-speed processing effectively in which processing time for each task is changed by roughly detecting its completion. Using this method, a high-speed processing circuit with a low error rate can be designed. The error rate is controllable, and a circuit design method to minimize the error rate is also presented in this paper. To confirm the effectiveness of our proposal, a ripple-carry adder (RCA), 2-dimensional discrete cosine transform (2D-DCT) circuit, and histogram of oriented gradients (HOG) feature calculation circuit are evaluated. Effective clock periods of these circuits obtained by our method with around 1% error rate are improved about 64%, 6%, and 12%, respectively, compared with circuits without error. Furthermore, the impact of the miscalculation on a video monitoring service using an object detection application is investigated. As a result, more than 99% of detection points required to be obtained are detected, and it is confirmed the miscalculation hardly degrades the service quality.},
keywords={},
doi={10.1587/transele.2020CDP0007},
ISSN={1745-1353},
month={July},}

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TY - JOUR
TI - Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism
T2 - IEICE TRANSACTIONS on Electronics
SP - 309
EP - 318
AU - Yuta UKON
AU - Shimpei SATO
AU - Atsushi TAKAHASHI
PY - 2021
DO - 10.1587/transele.2020CDP0007
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E104-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2021
AB - Advanced information-processing services such as computer vision require a high-performance digital circuit to perform high-load processing at high speed. To achieve high-speed processing, several image-processing applications use an approximate computing technique to reduce idle time of the circuit. However, it is difficult to design the high-speed image-processing circuit while controlling the error rate so as not to degrade service quality, and this technique is used for only a few applications. In this paper, we propose a method that achieves high-speed processing effectively in which processing time for each task is changed by roughly detecting its completion. Using this method, a high-speed processing circuit with a low error rate can be designed. The error rate is controllable, and a circuit design method to minimize the error rate is also presented in this paper. To confirm the effectiveness of our proposal, a ripple-carry adder (RCA), 2-dimensional discrete cosine transform (2D-DCT) circuit, and histogram of oriented gradients (HOG) feature calculation circuit are evaluated. Effective clock periods of these circuits obtained by our method with around 1% error rate are improved about 64%, 6%, and 12%, respectively, compared with circuits without error. Furthermore, the impact of the miscalculation on a video monitoring service using an object detection application is investigated. As a result, more than 99% of detection points required to be obtained are detected, and it is confirmed the miscalculation hardly degrades the service quality.
ER -

IEICE TRANSACTIONS on Electronics