A Metadata Prefetching Mechanism for Hybrid Memory Architectures

Shunsuke TSUKADA; Hikaru TAKAYASHIKI; Masayuki SATO; Kazuhiko KOMATSU; Hiroaki KOBAYASHI

doi:10.1587/transele.2021LHP0004

IEICE TRANSACTIONS on Electronics

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A Metadata Prefetching Mechanism for Hybrid Memory Architectures

Shunsuke TSUKADA, Hikaru TAKAYASHIKI, Masayuki SATO, Kazuhiko KOMATSU, Hiroaki KOBAYASHI

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Summary :

A hybrid memory architecture (HMA) that consists of some distinct memory devices is expected to achieve a good balance between high performance and large capacity. Unlike conventional memory architectures, the HMA needs the metadata for data management since the data are migrated between the memory devices during the execution of an application. The memory controller caches the metadata to avoid accessing the memory devices for the metadata reference. However, as the amount of the metadata increases in proportion to the size of the HMA, the memory controller needs to handle a large amount of metadata. As a result, the memory controller cannot cache all the metadata and increases the number of metadata references. This results in an increase in the access latency to reach the target data and degrades the performance. To solve this problem, this paper proposes a metadata prefetching mechanism for HMAs. The proposed mechanism loads the metadata needed in the near future by prefetching. Moreover, to increase the effect of the metadata prefetching, the proposed mechanism predicts the metadata used in the near future based on an address difference that is the difference between two consecutive access addresses. The evaluation results show that the proposed metadata prefetching mechanism can improve the instructions per cycle by up to 44% and 9% on average.

Publication: IEICE TRANSACTIONS on Electronics Vol.E105-C No.6 pp.232-243

Publication Date: 2022/06/01

Publicized: 2021/12/03

Online ISSN: 1745-1353

DOI: 10.1587/transele.2021LHP0004

Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips)

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Authors

Shunsuke TSUKADA
  Tohoku University
Hikaru TAKAYASHIKI
  Tohoku University
Masayuki SATO
  Tohoku University
Kazuhiko KOMATSU
  Tohoku University
Hiroaki KOBAYASHI
  Tohoku University

Keyword

hybrid memory architecture, metadata, prefetch, address difference, performance

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Shunsuke TSUKADA, Hikaru TAKAYASHIKI, Masayuki SATO, Kazuhiko KOMATSU, Hiroaki KOBAYASHI, "A Metadata Prefetching Mechanism for Hybrid Memory Architectures" in IEICE TRANSACTIONS on Electronics, vol. E105-C, no. 6, pp. 232-243, June 2022, doi: 10.1587/transele.2021LHP0004.
Abstract: A hybrid memory architecture (HMA) that consists of some distinct memory devices is expected to achieve a good balance between high performance and large capacity. Unlike conventional memory architectures, the HMA needs the metadata for data management since the data are migrated between the memory devices during the execution of an application. The memory controller caches the metadata to avoid accessing the memory devices for the metadata reference. However, as the amount of the metadata increases in proportion to the size of the HMA, the memory controller needs to handle a large amount of metadata. As a result, the memory controller cannot cache all the metadata and increases the number of metadata references. This results in an increase in the access latency to reach the target data and degrades the performance. To solve this problem, this paper proposes a metadata prefetching mechanism for HMAs. The proposed mechanism loads the metadata needed in the near future by prefetching. Moreover, to increase the effect of the metadata prefetching, the proposed mechanism predicts the metadata used in the near future based on an address difference that is the difference between two consecutive access addresses. The evaluation results show that the proposed metadata prefetching mechanism can improve the instructions per cycle by up to 44% and 9% on average.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2021LHP0004/_p

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@ARTICLE{e105-c_6_232,
author={Shunsuke TSUKADA, Hikaru TAKAYASHIKI, Masayuki SATO, Kazuhiko KOMATSU, Hiroaki KOBAYASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Metadata Prefetching Mechanism for Hybrid Memory Architectures},
year={2022},
volume={E105-C},
number={6},
pages={232-243},
abstract={A hybrid memory architecture (HMA) that consists of some distinct memory devices is expected to achieve a good balance between high performance and large capacity. Unlike conventional memory architectures, the HMA needs the metadata for data management since the data are migrated between the memory devices during the execution of an application. The memory controller caches the metadata to avoid accessing the memory devices for the metadata reference. However, as the amount of the metadata increases in proportion to the size of the HMA, the memory controller needs to handle a large amount of metadata. As a result, the memory controller cannot cache all the metadata and increases the number of metadata references. This results in an increase in the access latency to reach the target data and degrades the performance. To solve this problem, this paper proposes a metadata prefetching mechanism for HMAs. The proposed mechanism loads the metadata needed in the near future by prefetching. Moreover, to increase the effect of the metadata prefetching, the proposed mechanism predicts the metadata used in the near future based on an address difference that is the difference between two consecutive access addresses. The evaluation results show that the proposed metadata prefetching mechanism can improve the instructions per cycle by up to 44% and 9% on average.},
keywords={},
doi={10.1587/transele.2021LHP0004},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - A Metadata Prefetching Mechanism for Hybrid Memory Architectures
T2 - IEICE TRANSACTIONS on Electronics
SP - 232
EP - 243
AU - Shunsuke TSUKADA
AU - Hikaru TAKAYASHIKI
AU - Masayuki SATO
AU - Kazuhiko KOMATSU
AU - Hiroaki KOBAYASHI
PY - 2022
DO - 10.1587/transele.2021LHP0004
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E105-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2022
AB - A hybrid memory architecture (HMA) that consists of some distinct memory devices is expected to achieve a good balance between high performance and large capacity. Unlike conventional memory architectures, the HMA needs the metadata for data management since the data are migrated between the memory devices during the execution of an application. The memory controller caches the metadata to avoid accessing the memory devices for the metadata reference. However, as the amount of the metadata increases in proportion to the size of the HMA, the memory controller needs to handle a large amount of metadata. As a result, the memory controller cannot cache all the metadata and increases the number of metadata references. This results in an increase in the access latency to reach the target data and degrades the performance. To solve this problem, this paper proposes a metadata prefetching mechanism for HMAs. The proposed mechanism loads the metadata needed in the near future by prefetching. Moreover, to increase the effect of the metadata prefetching, the proposed mechanism predicts the metadata used in the near future based on an address difference that is the difference between two consecutive access addresses. The evaluation results show that the proposed metadata prefetching mechanism can improve the instructions per cycle by up to 44% and 9% on average.
ER -

IEICE TRANSACTIONS on Electronics