IEICE TRANSACTIONS on Electronics
Ka-Band Stacked-FET Power Amplifier IC with Adaptively Controlled Gate Capacitor and Two-Step Adaptive Bias Circuit in 45-nm SOI CMOS
Summary :
This paper presents a Ka-band high-efficiency power amplifier (PA) with a novel adaptively controlled gate capacitor circuit and a two-step adaptive bias circuit for 5th generation (5G) mobile terminal applications fabricated using a 45-nm silicon on insulator (SOI) CMOS process. The PA adopts a stacked FET structure to increase the output power because of the low breakdown voltage issue of scaled MOSFETs. The novel adaptive gate capacitor circuit properly controls the RF swing for each stacked FET to achieve high efficiency in the several-dB back-off region. Further, the novel two-step adaptive bias circuit effectively controls the gate voltage for each stacked FET for high linearity and high back-off efficiency. At a supply voltage of 4 V, the fabricated PA has exhibited a saturated output power of 20.0 dBm, a peak power added efficiency (PAE) of 42.7%, a 3dB back-off efficiency of 32.7%, a 6dB back-off efficiency of 22.7%, and a gain of 15.6 dB. The effective PA area was 0.82 mm by 0.74 mm.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E106-C No.7 pp.382-390
- Publication Date
- 2023/07/01
- Publicized
- 2023/01/12
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2022CDP0002
- Type of Manuscript
- Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
- Category
Authors
Tsuyoshi SUGIURA
Waseda University
Toshihiko YOSHIMASU
Waseda University
Keyword
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Tsuyoshi SUGIURA, Toshihiko YOSHIMASU, "Ka-Band Stacked-FET Power Amplifier IC with Adaptively Controlled Gate Capacitor and Two-Step Adaptive Bias Circuit in 45-nm SOI CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 7, pp. 382-390, July 2023, doi: 10.1587/transele.2022CDP0002.
Abstract: This paper presents a Ka-band high-efficiency power amplifier (PA) with a novel adaptively controlled gate capacitor circuit and a two-step adaptive bias circuit for 5th generation (5G) mobile terminal applications fabricated using a 45-nm silicon on insulator (SOI) CMOS process. The PA adopts a stacked FET structure to increase the output power because of the low breakdown voltage issue of scaled MOSFETs. The novel adaptive gate capacitor circuit properly controls the RF swing for each stacked FET to achieve high efficiency in the several-dB back-off region. Further, the novel two-step adaptive bias circuit effectively controls the gate voltage for each stacked FET for high linearity and high back-off efficiency. At a supply voltage of 4 V, the fabricated PA has exhibited a saturated output power of 20.0 dBm, a peak power added efficiency (PAE) of 42.7%, a 3dB back-off efficiency of 32.7%, a 6dB back-off efficiency of 22.7%, and a gain of 15.6 dB. The effective PA area was 0.82 mm by 0.74 mm.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022CDP0002/_p
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@ARTICLE{e106-c_7_382,
author={Tsuyoshi SUGIURA, Toshihiko YOSHIMASU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Ka-Band Stacked-FET Power Amplifier IC with Adaptively Controlled Gate Capacitor and Two-Step Adaptive Bias Circuit in 45-nm SOI CMOS},
year={2023},
volume={E106-C},
number={7},
pages={382-390},
abstract={This paper presents a Ka-band high-efficiency power amplifier (PA) with a novel adaptively controlled gate capacitor circuit and a two-step adaptive bias circuit for 5th generation (5G) mobile terminal applications fabricated using a 45-nm silicon on insulator (SOI) CMOS process. The PA adopts a stacked FET structure to increase the output power because of the low breakdown voltage issue of scaled MOSFETs. The novel adaptive gate capacitor circuit properly controls the RF swing for each stacked FET to achieve high efficiency in the several-dB back-off region. Further, the novel two-step adaptive bias circuit effectively controls the gate voltage for each stacked FET for high linearity and high back-off efficiency. At a supply voltage of 4 V, the fabricated PA has exhibited a saturated output power of 20.0 dBm, a peak power added efficiency (PAE) of 42.7%, a 3dB back-off efficiency of 32.7%, a 6dB back-off efficiency of 22.7%, and a gain of 15.6 dB. The effective PA area was 0.82 mm by 0.74 mm.},
keywords={},
doi={10.1587/transele.2022CDP0002},
ISSN={1745-1353},
month={July},}
Copy
TY - JOUR
TI - Ka-Band Stacked-FET Power Amplifier IC with Adaptively Controlled Gate Capacitor and Two-Step Adaptive Bias Circuit in 45-nm SOI CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 382
EP - 390
AU - Tsuyoshi SUGIURA
AU - Toshihiko YOSHIMASU
PY - 2023
DO - 10.1587/transele.2022CDP0002
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2023
AB - This paper presents a Ka-band high-efficiency power amplifier (PA) with a novel adaptively controlled gate capacitor circuit and a two-step adaptive bias circuit for 5th generation (5G) mobile terminal applications fabricated using a 45-nm silicon on insulator (SOI) CMOS process. The PA adopts a stacked FET structure to increase the output power because of the low breakdown voltage issue of scaled MOSFETs. The novel adaptive gate capacitor circuit properly controls the RF swing for each stacked FET to achieve high efficiency in the several-dB back-off region. Further, the novel two-step adaptive bias circuit effectively controls the gate voltage for each stacked FET for high linearity and high back-off efficiency. At a supply voltage of 4 V, the fabricated PA has exhibited a saturated output power of 20.0 dBm, a peak power added efficiency (PAE) of 42.7%, a 3dB back-off efficiency of 32.7%, a 6dB back-off efficiency of 22.7%, and a gain of 15.6 dB. The effective PA area was 0.82 mm by 0.74 mm.
ER -
English
