IEICE TRANSACTIONS on Electronics
A Fully Analog Deep Neural Network Inference Accelerator with Pipeline Registers Based on Master-Slave Switched Capacitors
Summary :
A fully analog pipelined deep neural network (DNN) accelerator is proposed, which is constructed by using pipeline registers based on master-slave switched capacitors. The idea of the master-slave switched capacitors is an analog equivalent of the delayed flip-flop (D-FF) which has been used as a digital pipeline register. To estimate the performance of the pipeline register, it is applied to a conventional DNN which performs non-pipeline operation. Compared with the conventional DNN, the cycle time is reduced by 61.5% and data rate is increased by 160%. The accuracy reaches 99.6% in MNIST classification test. The energy consumption per classification is reduced by 88.2% to 0.128µJ, achieving an energy efficiency of 1.05TOPS/W and a throughput of 0.538TOPS in 180nm technology node.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E106-C No.9 pp.477-485
- Publication Date
- 2023/09/01
- Publicized
- 2023/03/08
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2022ECP5049
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Yaxin MEI
Waseda University
Takashi OHSAWA
Waseda University
Keyword
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Yaxin MEI, Takashi OHSAWA, "A Fully Analog Deep Neural Network Inference Accelerator with Pipeline Registers Based on Master-Slave Switched Capacitors" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 9, pp. 477-485, September 2023, doi: 10.1587/transele.2022ECP5049.
Abstract: A fully analog pipelined deep neural network (DNN) accelerator is proposed, which is constructed by using pipeline registers based on master-slave switched capacitors. The idea of the master-slave switched capacitors is an analog equivalent of the delayed flip-flop (D-FF) which has been used as a digital pipeline register. To estimate the performance of the pipeline register, it is applied to a conventional DNN which performs non-pipeline operation. Compared with the conventional DNN, the cycle time is reduced by 61.5% and data rate is increased by 160%. The accuracy reaches 99.6% in MNIST classification test. The energy consumption per classification is reduced by 88.2% to 0.128µJ, achieving an energy efficiency of 1.05TOPS/W and a throughput of 0.538TOPS in 180nm technology node.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022ECP5049/_p
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@ARTICLE{e106-c_9_477,
author={Yaxin MEI, Takashi OHSAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Fully Analog Deep Neural Network Inference Accelerator with Pipeline Registers Based on Master-Slave Switched Capacitors},
year={2023},
volume={E106-C},
number={9},
pages={477-485},
abstract={A fully analog pipelined deep neural network (DNN) accelerator is proposed, which is constructed by using pipeline registers based on master-slave switched capacitors. The idea of the master-slave switched capacitors is an analog equivalent of the delayed flip-flop (D-FF) which has been used as a digital pipeline register. To estimate the performance of the pipeline register, it is applied to a conventional DNN which performs non-pipeline operation. Compared with the conventional DNN, the cycle time is reduced by 61.5% and data rate is increased by 160%. The accuracy reaches 99.6% in MNIST classification test. The energy consumption per classification is reduced by 88.2% to 0.128µJ, achieving an energy efficiency of 1.05TOPS/W and a throughput of 0.538TOPS in 180nm technology node.},
keywords={},
doi={10.1587/transele.2022ECP5049},
ISSN={1745-1353},
month={September},}
Copy
TY - JOUR
TI - A Fully Analog Deep Neural Network Inference Accelerator with Pipeline Registers Based on Master-Slave Switched Capacitors
T2 - IEICE TRANSACTIONS on Electronics
SP - 477
EP - 485
AU - Yaxin MEI
AU - Takashi OHSAWA
PY - 2023
DO - 10.1587/transele.2022ECP5049
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2023
AB - A fully analog pipelined deep neural network (DNN) accelerator is proposed, which is constructed by using pipeline registers based on master-slave switched capacitors. The idea of the master-slave switched capacitors is an analog equivalent of the delayed flip-flop (D-FF) which has been used as a digital pipeline register. To estimate the performance of the pipeline register, it is applied to a conventional DNN which performs non-pipeline operation. Compared with the conventional DNN, the cycle time is reduced by 61.5% and data rate is increased by 160%. The accuracy reaches 99.6% in MNIST classification test. The energy consumption per classification is reduced by 88.2% to 0.128µJ, achieving an energy efficiency of 1.05TOPS/W and a throughput of 0.538TOPS in 180nm technology node.
ER -
English
