IEICE TRANSACTIONS on Electronics
Design Considerations on Power, Performance, Reliability and Yield in 3D NAND Technology
Summary :
This paper discusses design challenges and possible solutions for 3D NAND. A 3D NAND array inherently has a larger parasitic capacitance and thereby critical area in terms of product yield. To mitigate such issues associated with 3D NAND technology, array control and divided array architecture for improving reliability and yield and for reducing area overhead, program time, energy per bit and array noise are proposed.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E101-C No.1 pp.78-81
- Publication Date
- 2018/01/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E101.C.78
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Toru TANZAWA
Shizuoka University
Keyword
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Toru TANZAWA, "Design Considerations on Power, Performance, Reliability and Yield in 3D NAND Technology" in IEICE TRANSACTIONS on Electronics,
vol. E101-C, no. 1, pp. 78-81, January 2018, doi: 10.1587/transele.E101.C.78.
Abstract: This paper discusses design challenges and possible solutions for 3D NAND. A 3D NAND array inherently has a larger parasitic capacitance and thereby critical area in terms of product yield. To mitigate such issues associated with 3D NAND technology, array control and divided array architecture for improving reliability and yield and for reducing area overhead, program time, energy per bit and array noise are proposed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E101.C.78/_p
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@ARTICLE{e101-c_1_78,
author={Toru TANZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design Considerations on Power, Performance, Reliability and Yield in 3D NAND Technology},
year={2018},
volume={E101-C},
number={1},
pages={78-81},
abstract={This paper discusses design challenges and possible solutions for 3D NAND. A 3D NAND array inherently has a larger parasitic capacitance and thereby critical area in terms of product yield. To mitigate such issues associated with 3D NAND technology, array control and divided array architecture for improving reliability and yield and for reducing area overhead, program time, energy per bit and array noise are proposed.},
keywords={},
doi={10.1587/transele.E101.C.78},
ISSN={1745-1353},
month={January},}
Copy
TY - JOUR
TI - Design Considerations on Power, Performance, Reliability and Yield in 3D NAND Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 78
EP - 81
AU - Toru TANZAWA
PY - 2018
DO - 10.1587/transele.E101.C.78
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E101-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2018
AB - This paper discusses design challenges and possible solutions for 3D NAND. A 3D NAND array inherently has a larger parasitic capacitance and thereby critical area in terms of product yield. To mitigate such issues associated with 3D NAND technology, array control and divided array architecture for improving reliability and yield and for reducing area overhead, program time, energy per bit and array noise are proposed.
ER -
English
