Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java Bytecode

Pradeep RAO; Kazuaki MURAKAMI

doi:10.1587/transele.E92.C.1265

Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java Bytecode

Pradeep RAO, Kazuaki MURAKAMI

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Despite the prevalence of Java workloads across a variety of processor architectures, there is very little published data on the impact of the various processor design decisions on Java performance. We attribute the lack of data to the large design space resulting from the complexity of the modern superscalar processor and the additional complexities associated with executing Java bytecode using a virtual machine. To address this shortcoming, we use a statistically rigorous methodology to systematically quantify the the impact of the various processor microarchitecture parameters on Java execution performance. The adopted methodology enables efficient screening of significant factor effects in a large design space consisting of 35 factors (32-billion potential configurations) using merely 72 observations per benchmark application. We quantify and tabulate the significance of each of the 35 factors for 13 benchmark applications. While these tables provide various insights into Java performance, they consistently highlight the performance significance of the instruction delivery mechanism, especially the instruction cache and the ITLB design parameters. Furthermore, these tables enable the architect to identify processor bottlenecks for Java workloads by providing an estimate of the relative impact of various design decisions.

Publication: IEICE TRANSACTIONS on Electronics Vol.E92-C No.10 pp.1265-1275

Publication Date: 2009/10/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E92.C.1265

Type of Manuscript: Special Section PAPER (Special Section on Hardware and Software Technologies on Advanced Microprocessors)

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Pradeep RAO, Kazuaki MURAKAMI, "Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java Bytecode" in IEICE TRANSACTIONS on Electronics, vol. E92-C, no. 10, pp. 1265-1275, October 2009, doi: 10.1587/transele.E92.C.1265.
Abstract: Despite the prevalence of Java workloads across a variety of processor architectures, there is very little published data on the impact of the various processor design decisions on Java performance. We attribute the lack of data to the large design space resulting from the complexity of the modern superscalar processor and the additional complexities associated with executing Java bytecode using a virtual machine. To address this shortcoming, we use a statistically rigorous methodology to systematically quantify the the impact of the various processor microarchitecture parameters on Java execution performance. The adopted methodology enables efficient screening of significant factor effects in a large design space consisting of 35 factors (32-billion potential configurations) using merely 72 observations per benchmark application. We quantify and tabulate the significance of each of the 35 factors for 13 benchmark applications. While these tables provide various insights into Java performance, they consistently highlight the performance significance of the instruction delivery mechanism, especially the instruction cache and the ITLB design parameters. Furthermore, these tables enable the architect to identify processor bottlenecks for Java workloads by providing an estimate of the relative impact of various design decisions.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1265/_p

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@ARTICLE{e92-c_10_1265,
author={Pradeep RAO, Kazuaki MURAKAMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java Bytecode},
year={2009},
volume={E92-C},
number={10},
pages={1265-1275},
abstract={Despite the prevalence of Java workloads across a variety of processor architectures, there is very little published data on the impact of the various processor design decisions on Java performance. We attribute the lack of data to the large design space resulting from the complexity of the modern superscalar processor and the additional complexities associated with executing Java bytecode using a virtual machine. To address this shortcoming, we use a statistically rigorous methodology to systematically quantify the the impact of the various processor microarchitecture parameters on Java execution performance. The adopted methodology enables efficient screening of significant factor effects in a large design space consisting of 35 factors (32-billion potential configurations) using merely 72 observations per benchmark application. We quantify and tabulate the significance of each of the 35 factors for 13 benchmark applications. While these tables provide various insights into Java performance, they consistently highlight the performance significance of the instruction delivery mechanism, especially the instruction cache and the ITLB design parameters. Furthermore, these tables enable the architect to identify processor bottlenecks for Java workloads by providing an estimate of the relative impact of various design decisions.},
keywords={},
doi={10.1587/transele.E92.C.1265},
ISSN={1745-1353},
month={October},}

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TY - JOUR
TI - Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java Bytecode
T2 - IEICE TRANSACTIONS on Electronics
SP - 1265
EP - 1275
AU - Pradeep RAO
AU - Kazuaki MURAKAMI
PY - 2009
DO - 10.1587/transele.E92.C.1265
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2009
AB - Despite the prevalence of Java workloads across a variety of processor architectures, there is very little published data on the impact of the various processor design decisions on Java performance. We attribute the lack of data to the large design space resulting from the complexity of the modern superscalar processor and the additional complexities associated with executing Java bytecode using a virtual machine. To address this shortcoming, we use a statistically rigorous methodology to systematically quantify the the impact of the various processor microarchitecture parameters on Java execution performance. The adopted methodology enables efficient screening of significant factor effects in a large design space consisting of 35 factors (32-billion potential configurations) using merely 72 observations per benchmark application. We quantify and tabulate the significance of each of the 35 factors for 13 benchmark applications. While these tables provide various insights into Java performance, they consistently highlight the performance significance of the instruction delivery mechanism, especially the instruction cache and the ITLB design parameters. Furthermore, these tables enable the architect to identify processor bottlenecks for Java workloads by providing an estimate of the relative impact of various design decisions.
ER -