IEICE TRANSACTIONS on Electronics
A Harmonic-Free All Digital Delay-Locked Loop Using an Improved Fast-Locking Successive Approximation Register-Controlled Scheme
Summary :
This paper proposes a novel delay-locked loop (DLL) with fast-locking property. The improved fast-locking successive approximation register-controlled (IFSAR) scheme can decrease the locking time to n+4 periods and be harmonic-free, where n is the bits' number of the control code for a delay line. According to the simulation result in 180 nm CMOS technology, the DLL can cover the operating range from 70 MHz to 500 MHz and dissipate 10.44 mW at 500 MHz.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.12 pp.1541-1544
- Publication Date
- 2009/12/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.1541
- Type of Manuscript
- BRIEF PAPER
- Category
- Integrated Electronics
Authors
Keyword
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Kai HUANG, Zhikuang CAI, Xin CHEN, Longxing SHI, "A Harmonic-Free All Digital Delay-Locked Loop Using an Improved Fast-Locking Successive Approximation Register-Controlled Scheme" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 12, pp. 1541-1544, December 2009, doi: 10.1587/transele.E92.C.1541.
Abstract: This paper proposes a novel delay-locked loop (DLL) with fast-locking property. The improved fast-locking successive approximation register-controlled (IFSAR) scheme can decrease the locking time to n+4 periods and be harmonic-free, where n is the bits' number of the control code for a delay line. According to the simulation result in 180 nm CMOS technology, the DLL can cover the operating range from 70 MHz to 500 MHz and dissipate 10.44 mW at 500 MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1541/_p
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@ARTICLE{e92-c_12_1541,
author={Kai HUANG, Zhikuang CAI, Xin CHEN, Longxing SHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Harmonic-Free All Digital Delay-Locked Loop Using an Improved Fast-Locking Successive Approximation Register-Controlled Scheme},
year={2009},
volume={E92-C},
number={12},
pages={1541-1544},
abstract={This paper proposes a novel delay-locked loop (DLL) with fast-locking property. The improved fast-locking successive approximation register-controlled (IFSAR) scheme can decrease the locking time to n+4 periods and be harmonic-free, where n is the bits' number of the control code for a delay line. According to the simulation result in 180 nm CMOS technology, the DLL can cover the operating range from 70 MHz to 500 MHz and dissipate 10.44 mW at 500 MHz.},
keywords={},
doi={10.1587/transele.E92.C.1541},
ISSN={1745-1353},
month={December},}
Copy
TY - JOUR
TI - A Harmonic-Free All Digital Delay-Locked Loop Using an Improved Fast-Locking Successive Approximation Register-Controlled Scheme
T2 - IEICE TRANSACTIONS on Electronics
SP - 1541
EP - 1544
AU - Kai HUANG
AU - Zhikuang CAI
AU - Xin CHEN
AU - Longxing SHI
PY - 2009
DO - 10.1587/transele.E92.C.1541
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2009
AB - This paper proposes a novel delay-locked loop (DLL) with fast-locking property. The improved fast-locking successive approximation register-controlled (IFSAR) scheme can decrease the locking time to n+4 periods and be harmonic-free, where n is the bits' number of the control code for a delay line. According to the simulation result in 180 nm CMOS technology, the DLL can cover the operating range from 70 MHz to 500 MHz and dissipate 10.44 mW at 500 MHz.
ER -
English
