IEICE TRANSACTIONS on Electronics
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture
Summary :
This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks to transfer context-ID bits. As a result, hardware utilization ratio decreases, since it is very difficult to map different contexts, area efficiently. It also increases the context switching power, area and static power of the context-ID tracks. The proposed MC-FPGA uses the same wires to transfer both data and context-ID bits from cell to cell. As a result, programs can be mapped area efficiently by partitioning them into different contexts. An asynchronous multi-context logic block architecture to increase the processing speed of the multiple contexts is also proposed. The proposed MC-FPGA is fabricated using 6-metal 1-poly CMOS design rules. The data and context-ID transfer delays are measured to be 2.03ns and 2.26ns respectively. We achieved 30% processing time reduction for the SAD based correspondance search algorithm.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.4 pp.539-549
- Publication Date
- 2009/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.539
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA, "Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 539-549, April 2009, doi: 10.1587/transele.E92.C.539.
Abstract: This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks to transfer context-ID bits. As a result, hardware utilization ratio decreases, since it is very difficult to map different contexts, area efficiently. It also increases the context switching power, area and static power of the context-ID tracks. The proposed MC-FPGA uses the same wires to transfer both data and context-ID bits from cell to cell. As a result, programs can be mapped area efficiently by partitioning them into different contexts. An asynchronous multi-context logic block architecture to increase the processing speed of the multiple contexts is also proposed. The proposed MC-FPGA is fabricated using 6-metal 1-poly CMOS design rules. The data and context-ID transfer delays are measured to be 2.03ns and 2.26ns respectively. We achieved 30% processing time reduction for the SAD based correspondance search algorithm.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.539/_p
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@ARTICLE{e92-c_4_539,
author={Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture},
year={2009},
volume={E92-C},
number={4},
pages={539-549},
abstract={This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks to transfer context-ID bits. As a result, hardware utilization ratio decreases, since it is very difficult to map different contexts, area efficiently. It also increases the context switching power, area and static power of the context-ID tracks. The proposed MC-FPGA uses the same wires to transfer both data and context-ID bits from cell to cell. As a result, programs can be mapped area efficiently by partitioning them into different contexts. An asynchronous multi-context logic block architecture to increase the processing speed of the multiple contexts is also proposed. The proposed MC-FPGA is fabricated using 6-metal 1-poly CMOS design rules. The data and context-ID transfer delays are measured to be 2.03ns and 2.26ns respectively. We achieved 30% processing time reduction for the SAD based correspondance search algorithm.},
keywords={},
doi={10.1587/transele.E92.C.539},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 539
EP - 549
AU - Hasitha Muthumala WAIDYASOORIYA
AU - Masanori HARIYAMA
AU - Michitaka KAMEYAMA
PY - 2009
DO - 10.1587/transele.E92.C.539
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks to transfer context-ID bits. As a result, hardware utilization ratio decreases, since it is very difficult to map different contexts, area efficiently. It also increases the context switching power, area and static power of the context-ID tracks. The proposed MC-FPGA uses the same wires to transfer both data and context-ID bits from cell to cell. As a result, programs can be mapped area efficiently by partitioning them into different contexts. An asynchronous multi-context logic block architecture to increase the processing speed of the multiple contexts is also proposed. The proposed MC-FPGA is fabricated using 6-metal 1-poly CMOS design rules. The data and context-ID transfer delays are measured to be 2.03ns and 2.26ns respectively. We achieved 30% processing time reduction for the SAD based correspondance search algorithm.
ER -
English
