A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder

Gang HE; Dajiang ZHOU; Jinjia ZHOU; Tianruo ZHANG; Satoshi GOTO

doi:10.1587/transele.E94.C.419

A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder

Gang HE, Dajiang ZHOU, Jinjia ZHOU, Tianruo ZHANG, Satoshi GOTO

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Intra coding in H.264/AVC significantly enhances video compression efficiency. However, due to the high data dependency of intra prediction in H.264, both pipelining and parallel processing techniques are limited to be applied. Moreover, it is difficult to get high hardware utilization and throughput because of the long block/MB-level reconstruction loops. This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 40962160 encoding can be achieved with negligible quality loss. 1616 prediction engine and 88 prediction engine work parallel for prediction and coefficients generating. A reordering interlaced reconstruction is also designed for fully pipelined architecture. It takes only 160 cycles to process one macroblock (MB). Hardware utilization of prediction and reconstruction modules is almost 100%. Furthermore, PE-reusable 88 intra predictor and hybrid SAD & SATD mode decision are proposed to save hardware cost. The design is implemented by 90 nm CMOS technology with 113.2 k gates and can encode 40962160 video sequences at 60 fps with operation frequency of 332 MHz.

Publication: IEICE TRANSACTIONS on Electronics Vol.E94-C No.4 pp.419-427

Publication Date: 2011/04/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E94.C.419

Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)

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Gang HE, Dajiang ZHOU, Jinjia ZHOU, Tianruo ZHANG, Satoshi GOTO, "A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder" in IEICE TRANSACTIONS on Electronics, vol. E94-C, no. 4, pp. 419-427, April 2011, doi: 10.1587/transele.E94.C.419.
Abstract: Intra coding in H.264/AVC significantly enhances video compression efficiency. However, due to the high data dependency of intra prediction in H.264, both pipelining and parallel processing techniques are limited to be applied. Moreover, it is difficult to get high hardware utilization and throughput because of the long block/MB-level reconstruction loops. This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 40962160 encoding can be achieved with negligible quality loss. 1616 prediction engine and 88 prediction engine work parallel for prediction and coefficients generating. A reordering interlaced reconstruction is also designed for fully pipelined architecture. It takes only 160 cycles to process one macroblock (MB). Hardware utilization of prediction and reconstruction modules is almost 100%. Furthermore, PE-reusable 88 intra predictor and hybrid SAD & SATD mode decision are proposed to save hardware cost. The design is implemented by 90 nm CMOS technology with 113.2 k gates and can encode 40962160 video sequences at 60 fps with operation frequency of 332 MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.419/_p

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@ARTICLE{e94-c_4_419,
author={Gang HE, Dajiang ZHOU, Jinjia ZHOU, Tianruo ZHANG, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder},
year={2011},
volume={E94-C},
number={4},
pages={419-427},
abstract={Intra coding in H.264/AVC significantly enhances video compression efficiency. However, due to the high data dependency of intra prediction in H.264, both pipelining and parallel processing techniques are limited to be applied. Moreover, it is difficult to get high hardware utilization and throughput because of the long block/MB-level reconstruction loops. This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 40962160 encoding can be achieved with negligible quality loss. 1616 prediction engine and 88 prediction engine work parallel for prediction and coefficients generating. A reordering interlaced reconstruction is also designed for fully pipelined architecture. It takes only 160 cycles to process one macroblock (MB). Hardware utilization of prediction and reconstruction modules is almost 100%. Furthermore, PE-reusable 88 intra predictor and hybrid SAD & SATD mode decision are proposed to save hardware cost. The design is implemented by 90 nm CMOS technology with 113.2 k gates and can encode 40962160 video sequences at 60 fps with operation frequency of 332 MHz.},
keywords={},
doi={10.1587/transele.E94.C.419},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder
T2 - IEICE TRANSACTIONS on Electronics
SP - 419
EP - 427
AU - Gang HE
AU - Dajiang ZHOU
AU - Jinjia ZHOU
AU - Tianruo ZHANG
AU - Satoshi GOTO
PY - 2011
DO - 10.1587/transele.E94.C.419
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - Intra coding in H.264/AVC significantly enhances video compression efficiency. However, due to the high data dependency of intra prediction in H.264, both pipelining and parallel processing techniques are limited to be applied. Moreover, it is difficult to get high hardware utilization and throughput because of the long block/MB-level reconstruction loops. This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 40962160 encoding can be achieved with negligible quality loss. 1616 prediction engine and 88 prediction engine work parallel for prediction and coefficients generating. A reordering interlaced reconstruction is also designed for fully pipelined architecture. It takes only 160 cycles to process one macroblock (MB). Hardware utilization of prediction and reconstruction modules is almost 100%. Furthermore, PE-reusable 88 intra predictor and hybrid SAD & SATD mode decision are proposed to save hardware cost. The design is implemented by 90 nm CMOS technology with 113.2 k gates and can encode 40962160 video sequences at 60 fps with operation frequency of 332 MHz.
ER -