A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction

Xi ZHANG; Chongmin LI; Zhenyu LIU; Haixia WANG; Dongsheng WANG; Takeshi IKENAGA

doi:10.1587/transele.E94.C.468

A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction

Xi ZHANG, Chongmin LI, Zhenyu LIU, Haixia WANG, Dongsheng WANG, Takeshi IKENAGA

Full Text Views

0

Cite this

Summary :

Previous research illustrates that LRU replacement policy is not efficient when applications exhibit a distant re-reference interval. Recently RRIP policy is proposed to improve the performance for such kind of workloads. However, the lack of access recency information in RRIP confuses the replacement policy to make the accurate prediction. To enhance the robustness of RRIP for recency-friendly workloads, we propose an Dynamic Adaptive Insertion and Re-reference Prediction (DAI-RRP) policy which evicts data based on both re-reference prediction value and the access recency information. DAI-RRP makes adaptive adjustment on insertion position and prediction value for different access patterns, which makes the policy robust across different workloads and different phases. Simulation results show that DAI-RRP outperforms LRU and RRIP. For a single-core processor with a 1 MB 16-way set last-level cache (LLC), DAI-RRP reduces CPI over LRU and Dynamic RRIP by an average of 8.1% and 2.7% respectively. Evaluations on quad-core CMP with a 4 MB shared LLC show that DAI-RRP outperforms LRU and Dynamic RRIP (DRRIP) on the weighted speedup metric by an average of 8.1% and 15.7% respectively. Furthermore, compared to LRU, DAI-RRP consumes the similar hardware for 16-way cache, or even less hardware for high-associativity cache. In summary, the proposed policy is practical and can be easily integrated into existing hardware approximations of LRU.

Publication: IEICE TRANSACTIONS on Electronics Vol.E94-C No.4 pp.468-476

Publication Date: 2011/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E94.C.468

Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)

Category

Cite this

Copy

Xi ZHANG, Chongmin LI, Zhenyu LIU, Haixia WANG, Dongsheng WANG, Takeshi IKENAGA, "A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction" in IEICE TRANSACTIONS on Electronics, vol. E94-C, no. 4, pp. 468-476, April 2011, doi: 10.1587/transele.E94.C.468.
Abstract: Previous research illustrates that LRU replacement policy is not efficient when applications exhibit a distant re-reference interval. Recently RRIP policy is proposed to improve the performance for such kind of workloads. However, the lack of access recency information in RRIP confuses the replacement policy to make the accurate prediction. To enhance the robustness of RRIP for recency-friendly workloads, we propose an Dynamic Adaptive Insertion and Re-reference Prediction (DAI-RRP) policy which evicts data based on both re-reference prediction value and the access recency information. DAI-RRP makes adaptive adjustment on insertion position and prediction value for different access patterns, which makes the policy robust across different workloads and different phases. Simulation results show that DAI-RRP outperforms LRU and RRIP. For a single-core processor with a 1 MB 16-way set last-level cache (LLC), DAI-RRP reduces CPI over LRU and Dynamic RRIP by an average of 8.1% and 2.7% respectively. Evaluations on quad-core CMP with a 4 MB shared LLC show that DAI-RRP outperforms LRU and Dynamic RRIP (DRRIP) on the weighted speedup metric by an average of 8.1% and 15.7% respectively. Furthermore, compared to LRU, DAI-RRP consumes the similar hardware for 16-way cache, or even less hardware for high-associativity cache. In summary, the proposed policy is practical and can be easily integrated into existing hardware approximations of LRU.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.468/_p

Copy

@ARTICLE{e94-c_4_468,
author={Xi ZHANG, Chongmin LI, Zhenyu LIU, Haixia WANG, Dongsheng WANG, Takeshi IKENAGA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction},
year={2011},
volume={E94-C},
number={4},
pages={468-476},
abstract={Previous research illustrates that LRU replacement policy is not efficient when applications exhibit a distant re-reference interval. Recently RRIP policy is proposed to improve the performance for such kind of workloads. However, the lack of access recency information in RRIP confuses the replacement policy to make the accurate prediction. To enhance the robustness of RRIP for recency-friendly workloads, we propose an Dynamic Adaptive Insertion and Re-reference Prediction (DAI-RRP) policy which evicts data based on both re-reference prediction value and the access recency information. DAI-RRP makes adaptive adjustment on insertion position and prediction value for different access patterns, which makes the policy robust across different workloads and different phases. Simulation results show that DAI-RRP outperforms LRU and RRIP. For a single-core processor with a 1 MB 16-way set last-level cache (LLC), DAI-RRP reduces CPI over LRU and Dynamic RRIP by an average of 8.1% and 2.7% respectively. Evaluations on quad-core CMP with a 4 MB shared LLC show that DAI-RRP outperforms LRU and Dynamic RRIP (DRRIP) on the weighted speedup metric by an average of 8.1% and 15.7% respectively. Furthermore, compared to LRU, DAI-RRP consumes the similar hardware for 16-way cache, or even less hardware for high-associativity cache. In summary, the proposed policy is practical and can be easily integrated into existing hardware approximations of LRU.},
keywords={},
doi={10.1587/transele.E94.C.468},
ISSN={1745-1353},
month={April},}

Copy

TY - JOUR
TI - A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction
T2 - IEICE TRANSACTIONS on Electronics
SP - 468
EP - 476
AU - Xi ZHANG
AU - Chongmin LI
AU - Zhenyu LIU
AU - Haixia WANG
AU - Dongsheng WANG
AU - Takeshi IKENAGA
PY - 2011
DO - 10.1587/transele.E94.C.468
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - Previous research illustrates that LRU replacement policy is not efficient when applications exhibit a distant re-reference interval. Recently RRIP policy is proposed to improve the performance for such kind of workloads. However, the lack of access recency information in RRIP confuses the replacement policy to make the accurate prediction. To enhance the robustness of RRIP for recency-friendly workloads, we propose an Dynamic Adaptive Insertion and Re-reference Prediction (DAI-RRP) policy which evicts data based on both re-reference prediction value and the access recency information. DAI-RRP makes adaptive adjustment on insertion position and prediction value for different access patterns, which makes the policy robust across different workloads and different phases. Simulation results show that DAI-RRP outperforms LRU and RRIP. For a single-core processor with a 1 MB 16-way set last-level cache (LLC), DAI-RRP reduces CPI over LRU and Dynamic RRIP by an average of 8.1% and 2.7% respectively. Evaluations on quad-core CMP with a 4 MB shared LLC show that DAI-RRP outperforms LRU and Dynamic RRIP (DRRIP) on the weighted speedup metric by an average of 8.1% and 15.7% respectively. Furthermore, compared to LRU, DAI-RRP consumes the similar hardware for 16-way cache, or even less hardware for high-associativity cache. In summary, the proposed policy is practical and can be easily integrated into existing hardware approximations of LRU.
ER -