Impact of Floating Body Type DRAM with the Vertical MOSFET

Yuto NORIFUSA; Tetsuo ENDOH

doi:10.1587/transele.E94.C.705

Impact of Floating Body Type DRAM with the Vertical MOSFET

Yuto NORIFUSA, Tetsuo ENDOH

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Several kinds of capacitor-less DRAM cells based on planar SOI-MOSFET technology have been proposed and researched to overcome the integration limit of the conventional DRAM. In this paper, we propose the Floating Body type DRAM cell array architecture with the Vertical MOSFET and discuss its basic operation using a 3-D device simulator. In contrast to previous planar SOI-MOSFET technology, the Floating Body type DRAM with the Vertical MOSFET achieves a cell area of 4F² and obtain its floating body cell by isolating the body from the substrate vertically by the bottom-electrode. Therefore, the necessity for a SOI substrate is eliminated. In this paper, the cell array architecture of Floating Body type 1T-DRAM is proposed, and furthermore, the basic memory operations of read, write, and erase for Vertical type 1 transistor (1T) DRAM in the 45 nm technology node are shown. In addition, the retention and disturb characteristics of the Vertical type 1T-DRAM are discussed.

Publication: IEICE TRANSACTIONS on Electronics Vol.E94-C No.5 pp.705-711

Publication Date: 2011/05/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E94.C.705

Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)

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Yuto NORIFUSA, Tetsuo ENDOH, "Impact of Floating Body Type DRAM with the Vertical MOSFET" in IEICE TRANSACTIONS on Electronics, vol. E94-C, no. 5, pp. 705-711, May 2011, doi: 10.1587/transele.E94.C.705.
Abstract: Several kinds of capacitor-less DRAM cells based on planar SOI-MOSFET technology have been proposed and researched to overcome the integration limit of the conventional DRAM. In this paper, we propose the Floating Body type DRAM cell array architecture with the Vertical MOSFET and discuss its basic operation using a 3-D device simulator. In contrast to previous planar SOI-MOSFET technology, the Floating Body type DRAM with the Vertical MOSFET achieves a cell area of 4F² and obtain its floating body cell by isolating the body from the substrate vertically by the bottom-electrode. Therefore, the necessity for a SOI substrate is eliminated. In this paper, the cell array architecture of Floating Body type 1T-DRAM is proposed, and furthermore, the basic memory operations of read, write, and erase for Vertical type 1 transistor (1T) DRAM in the 45 nm technology node are shown. In addition, the retention and disturb characteristics of the Vertical type 1T-DRAM are discussed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.705/_p

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@ARTICLE{e94-c_5_705,
author={Yuto NORIFUSA, Tetsuo ENDOH, },
journal={IEICE TRANSACTIONS on Electronics},
title={Impact of Floating Body Type DRAM with the Vertical MOSFET},
year={2011},
volume={E94-C},
number={5},
pages={705-711},
abstract={Several kinds of capacitor-less DRAM cells based on planar SOI-MOSFET technology have been proposed and researched to overcome the integration limit of the conventional DRAM. In this paper, we propose the Floating Body type DRAM cell array architecture with the Vertical MOSFET and discuss its basic operation using a 3-D device simulator. In contrast to previous planar SOI-MOSFET technology, the Floating Body type DRAM with the Vertical MOSFET achieves a cell area of 4F² and obtain its floating body cell by isolating the body from the substrate vertically by the bottom-electrode. Therefore, the necessity for a SOI substrate is eliminated. In this paper, the cell array architecture of Floating Body type 1T-DRAM is proposed, and furthermore, the basic memory operations of read, write, and erase for Vertical type 1 transistor (1T) DRAM in the 45 nm technology node are shown. In addition, the retention and disturb characteristics of the Vertical type 1T-DRAM are discussed.},
keywords={},
doi={10.1587/transele.E94.C.705},
ISSN={1745-1353},
month={May},}

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TY - JOUR
TI - Impact of Floating Body Type DRAM with the Vertical MOSFET
T2 - IEICE TRANSACTIONS on Electronics
SP - 705
EP - 711
AU - Yuto NORIFUSA
AU - Tetsuo ENDOH
PY - 2011
DO - 10.1587/transele.E94.C.705
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2011
AB - Several kinds of capacitor-less DRAM cells based on planar SOI-MOSFET technology have been proposed and researched to overcome the integration limit of the conventional DRAM. In this paper, we propose the Floating Body type DRAM cell array architecture with the Vertical MOSFET and discuss its basic operation using a 3-D device simulator. In contrast to previous planar SOI-MOSFET technology, the Floating Body type DRAM with the Vertical MOSFET achieves a cell area of 4F² and obtain its floating body cell by isolating the body from the substrate vertically by the bottom-electrode. Therefore, the necessity for a SOI substrate is eliminated. In this paper, the cell array architecture of Floating Body type 1T-DRAM is proposed, and furthermore, the basic memory operations of read, write, and erase for Vertical type 1 transistor (1T) DRAM in the 45 nm technology node are shown. In addition, the retention and disturb characteristics of the Vertical type 1T-DRAM are discussed.
ER -