IEICE TRANSACTIONS on Electronics
Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC
Summary :
Hybrid wired/wireless on-chip network is a promising communication architecture for multi-/many-core SoC. For application-specific SoC design, it is important to design a dedicated on-chip network architecture according to the application-specific nature. In this paper, we propose a heuristic wireless link allocation algorithm for creating hybrid on-chip network architecture. The algorithm can eliminate the performance bottleneck by replacing multi-hop wired paths by high-bandwidth single-hop long-range wireless links. The simulation results show that the hybrid on-chip network designed by our algorithm improves the performance in terms of both communication delay and energy consumption significantly.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.4 pp.495-505
- Publication Date
- 2012/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.495
- Type of Manuscript
- Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
- Category
Authors
Keyword
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Shouyi YIN, Yang HU, Zhen ZHANG, Leibo LIU, Shaojun WEI, "Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 4, pp. 495-505, April 2012, doi: 10.1587/transele.E95.C.495.
Abstract: Hybrid wired/wireless on-chip network is a promising communication architecture for multi-/many-core SoC. For application-specific SoC design, it is important to design a dedicated on-chip network architecture according to the application-specific nature. In this paper, we propose a heuristic wireless link allocation algorithm for creating hybrid on-chip network architecture. The algorithm can eliminate the performance bottleneck by replacing multi-hop wired paths by high-bandwidth single-hop long-range wireless links. The simulation results show that the hybrid on-chip network designed by our algorithm improves the performance in terms of both communication delay and energy consumption significantly.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.495/_p
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@ARTICLE{e95-c_4_495,
author={Shouyi YIN, Yang HU, Zhen ZHANG, Leibo LIU, Shaojun WEI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC},
year={2012},
volume={E95-C},
number={4},
pages={495-505},
abstract={Hybrid wired/wireless on-chip network is a promising communication architecture for multi-/many-core SoC. For application-specific SoC design, it is important to design a dedicated on-chip network architecture according to the application-specific nature. In this paper, we propose a heuristic wireless link allocation algorithm for creating hybrid on-chip network architecture. The algorithm can eliminate the performance bottleneck by replacing multi-hop wired paths by high-bandwidth single-hop long-range wireless links. The simulation results show that the hybrid on-chip network designed by our algorithm improves the performance in terms of both communication delay and energy consumption significantly.},
keywords={},
doi={10.1587/transele.E95.C.495},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC
T2 - IEICE TRANSACTIONS on Electronics
SP - 495
EP - 505
AU - Shouyi YIN
AU - Yang HU
AU - Zhen ZHANG
AU - Leibo LIU
AU - Shaojun WEI
PY - 2012
DO - 10.1587/transele.E95.C.495
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2012
AB - Hybrid wired/wireless on-chip network is a promising communication architecture for multi-/many-core SoC. For application-specific SoC design, it is important to design a dedicated on-chip network architecture according to the application-specific nature. In this paper, we propose a heuristic wireless link allocation algorithm for creating hybrid on-chip network architecture. The algorithm can eliminate the performance bottleneck by replacing multi-hop wired paths by high-bandwidth single-hop long-range wireless links. The simulation results show that the hybrid on-chip network designed by our algorithm improves the performance in terms of both communication delay and energy consumption significantly.
ER -
English
