IEICE TRANSACTIONS on Electronics
Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips
Summary :
Network-on-Chips (NoCs) have been proposed as a solution for addressing the global communication challenges in System-on-Chip (SoC) architectures that are implemented in nanoscale technologies. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, power- efficient NoC topology that satisfies the application characteristics is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC topologies. We present a method which integrates partitioning into floorplanning phase to explore optimal clustering of cores during floorplanning with minimized link and switch power consumption. Based on the size of applications, we also present an Integer Linear Programming and a heuristic method to place switches and network interfaces on the floorplan. Then, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. We perform experiments on several SoC benchmarks and present a comparison with the latest work. For small applications, the NoC topologies synthesized by our method show large improvements in power consumption (27.54%), hop-count (4%) and running time (66%) on average. And for large applications, the synthesized topologies result in large power (31.77%), hop-count (29%) and running time (94.18%) on average.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.4 pp.534-545
- Publication Date
- 2012/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.534
- Type of Manuscript
- Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
- Category
Authors
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Wei ZHONG, Takeshi YOSHIMURA, Bei YU, Song CHEN, Sheqin DONG, Satoshi GOTO, "Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 4, pp. 534-545, April 2012, doi: 10.1587/transele.E95.C.534.
Abstract: Network-on-Chips (NoCs) have been proposed as a solution for addressing the global communication challenges in System-on-Chip (SoC) architectures that are implemented in nanoscale technologies. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, power- efficient NoC topology that satisfies the application characteristics is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC topologies. We present a method which integrates partitioning into floorplanning phase to explore optimal clustering of cores during floorplanning with minimized link and switch power consumption. Based on the size of applications, we also present an Integer Linear Programming and a heuristic method to place switches and network interfaces on the floorplan. Then, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. We perform experiments on several SoC benchmarks and present a comparison with the latest work. For small applications, the NoC topologies synthesized by our method show large improvements in power consumption (27.54%), hop-count (4%) and running time (66%) on average. And for large applications, the synthesized topologies result in large power (31.77%), hop-count (29%) and running time (94.18%) on average.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.534/_p
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@ARTICLE{e95-c_4_534,
author={Wei ZHONG, Takeshi YOSHIMURA, Bei YU, Song CHEN, Sheqin DONG, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips},
year={2012},
volume={E95-C},
number={4},
pages={534-545},
abstract={Network-on-Chips (NoCs) have been proposed as a solution for addressing the global communication challenges in System-on-Chip (SoC) architectures that are implemented in nanoscale technologies. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, power- efficient NoC topology that satisfies the application characteristics is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC topologies. We present a method which integrates partitioning into floorplanning phase to explore optimal clustering of cores during floorplanning with minimized link and switch power consumption. Based on the size of applications, we also present an Integer Linear Programming and a heuristic method to place switches and network interfaces on the floorplan. Then, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. We perform experiments on several SoC benchmarks and present a comparison with the latest work. For small applications, the NoC topologies synthesized by our method show large improvements in power consumption (27.54%), hop-count (4%) and running time (66%) on average. And for large applications, the synthesized topologies result in large power (31.77%), hop-count (29%) and running time (94.18%) on average.},
keywords={},
doi={10.1587/transele.E95.C.534},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips
T2 - IEICE TRANSACTIONS on Electronics
SP - 534
EP - 545
AU - Wei ZHONG
AU - Takeshi YOSHIMURA
AU - Bei YU
AU - Song CHEN
AU - Sheqin DONG
AU - Satoshi GOTO
PY - 2012
DO - 10.1587/transele.E95.C.534
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2012
AB - Network-on-Chips (NoCs) have been proposed as a solution for addressing the global communication challenges in System-on-Chip (SoC) architectures that are implemented in nanoscale technologies. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, power- efficient NoC topology that satisfies the application characteristics is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC topologies. We present a method which integrates partitioning into floorplanning phase to explore optimal clustering of cores during floorplanning with minimized link and switch power consumption. Based on the size of applications, we also present an Integer Linear Programming and a heuristic method to place switches and network interfaces on the floorplan. Then, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. We perform experiments on several SoC benchmarks and present a comparison with the latest work. For small applications, the NoC topologies synthesized by our method show large improvements in power consumption (27.54%), hop-count (4%) and running time (66%) on average. And for large applications, the synthesized topologies result in large power (31.77%), hop-count (29%) and running time (94.18%) on average.
ER -
English
