We have investigated the operational performance of an optical serial-to-parallel conversion scheme using a phase-shifted preamble handling optical packets formatted by differential phase shift keying (DPSK) for integrated optical serial-to-parallel converter (OSPC). The same architecture for on-off keyed signals, based on a transmitter-side preamble at the top of the packet and phase-shifted by π/2, which is then -π/2 phase-biased with a Mach-Zehnder delay interferometer (MZDI), is available for binary and differential PSK signals. The delay length of these signals is determined by the relative timing positions of the gated bit and a balanced receiver-side photodetector. We simulated the operational performance of this scheme and its tolerance against the degree of modulation and optical chirp, with our results showing that a phase shift of more than 0.94π is required in order to attain a suppression ratio in the OSPC output consistent with a bit error rate of less than 10-9 (based on the ratio of intensity of the extracted bit to the maximum peak intensity of the cancelled bits using a single-arm phase modulator). However, by using a Mach-Zehnder phase modulator, the modulation angle can be relaxed to about 0.36π. Experimental investigation of the OSPC showed that its functional tolerance with respect to the modulation angle agreed well with the simulated values. Finally, we performed optical label processing using the OSPC in conjunction with an address table, and our results confirmed the potential of the OSPC for use in label recognition.
Kotaro NEGISHI
Tokyo Institute of Technology
Hiroyuki UENOHARA
Tokyo Institute of Technology
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Kotaro NEGISHI, Hiroyuki UENOHARA, "Operational Performance of an Optical Serial-to-Parallel Converter Based on a Mach-Zehnder Delay Interferometer and a Phase-Shifted Preamble for DPSK-Formatted Signals" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 7, pp. 1012-1018, July 2013, doi: 10.1587/transele.E96.C.1012.
Abstract: We have investigated the operational performance of an optical serial-to-parallel conversion scheme using a phase-shifted preamble handling optical packets formatted by differential phase shift keying (DPSK) for integrated optical serial-to-parallel converter (OSPC). The same architecture for on-off keyed signals, based on a transmitter-side preamble at the top of the packet and phase-shifted by π/2, which is then -π/2 phase-biased with a Mach-Zehnder delay interferometer (MZDI), is available for binary and differential PSK signals. The delay length of these signals is determined by the relative timing positions of the gated bit and a balanced receiver-side photodetector. We simulated the operational performance of this scheme and its tolerance against the degree of modulation and optical chirp, with our results showing that a phase shift of more than 0.94π is required in order to attain a suppression ratio in the OSPC output consistent with a bit error rate of less than 10-9 (based on the ratio of intensity of the extracted bit to the maximum peak intensity of the cancelled bits using a single-arm phase modulator). However, by using a Mach-Zehnder phase modulator, the modulation angle can be relaxed to about 0.36π. Experimental investigation of the OSPC showed that its functional tolerance with respect to the modulation angle agreed well with the simulated values. Finally, we performed optical label processing using the OSPC in conjunction with an address table, and our results confirmed the potential of the OSPC for use in label recognition.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.1012/_p
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@ARTICLE{e96-c_7_1012,
author={Kotaro NEGISHI, Hiroyuki UENOHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Operational Performance of an Optical Serial-to-Parallel Converter Based on a Mach-Zehnder Delay Interferometer and a Phase-Shifted Preamble for DPSK-Formatted Signals},
year={2013},
volume={E96-C},
number={7},
pages={1012-1018},
abstract={We have investigated the operational performance of an optical serial-to-parallel conversion scheme using a phase-shifted preamble handling optical packets formatted by differential phase shift keying (DPSK) for integrated optical serial-to-parallel converter (OSPC). The same architecture for on-off keyed signals, based on a transmitter-side preamble at the top of the packet and phase-shifted by π/2, which is then -π/2 phase-biased with a Mach-Zehnder delay interferometer (MZDI), is available for binary and differential PSK signals. The delay length of these signals is determined by the relative timing positions of the gated bit and a balanced receiver-side photodetector. We simulated the operational performance of this scheme and its tolerance against the degree of modulation and optical chirp, with our results showing that a phase shift of more than 0.94π is required in order to attain a suppression ratio in the OSPC output consistent with a bit error rate of less than 10-9 (based on the ratio of intensity of the extracted bit to the maximum peak intensity of the cancelled bits using a single-arm phase modulator). However, by using a Mach-Zehnder phase modulator, the modulation angle can be relaxed to about 0.36π. Experimental investigation of the OSPC showed that its functional tolerance with respect to the modulation angle agreed well with the simulated values. Finally, we performed optical label processing using the OSPC in conjunction with an address table, and our results confirmed the potential of the OSPC for use in label recognition.},
keywords={},
doi={10.1587/transele.E96.C.1012},
ISSN={1745-1353},
month={July},}
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TY - JOUR
TI - Operational Performance of an Optical Serial-to-Parallel Converter Based on a Mach-Zehnder Delay Interferometer and a Phase-Shifted Preamble for DPSK-Formatted Signals
T2 - IEICE TRANSACTIONS on Electronics
SP - 1012
EP - 1018
AU - Kotaro NEGISHI
AU - Hiroyuki UENOHARA
PY - 2013
DO - 10.1587/transele.E96.C.1012
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2013
AB - We have investigated the operational performance of an optical serial-to-parallel conversion scheme using a phase-shifted preamble handling optical packets formatted by differential phase shift keying (DPSK) for integrated optical serial-to-parallel converter (OSPC). The same architecture for on-off keyed signals, based on a transmitter-side preamble at the top of the packet and phase-shifted by π/2, which is then -π/2 phase-biased with a Mach-Zehnder delay interferometer (MZDI), is available for binary and differential PSK signals. The delay length of these signals is determined by the relative timing positions of the gated bit and a balanced receiver-side photodetector. We simulated the operational performance of this scheme and its tolerance against the degree of modulation and optical chirp, with our results showing that a phase shift of more than 0.94π is required in order to attain a suppression ratio in the OSPC output consistent with a bit error rate of less than 10-9 (based on the ratio of intensity of the extracted bit to the maximum peak intensity of the cancelled bits using a single-arm phase modulator). However, by using a Mach-Zehnder phase modulator, the modulation angle can be relaxed to about 0.36π. Experimental investigation of the OSPC showed that its functional tolerance with respect to the modulation angle agreed well with the simulated values. Finally, we performed optical label processing using the OSPC in conjunction with an address table, and our results confirmed the potential of the OSPC for use in label recognition.
ER -