This paper presents a novel data compression method for testing integrated circuits within the framework of pattern run-length coding. The test set is firstly divided into 2n-length patterns where n is a natural number. Then the compatibility of each pattern, which can be an external type, or an internal type, is analyzed. At last, the codeword of each pattern is generated according to its analysis result. Experimental results for large ISCAS89 benchmarks show that the proposed method can obtain a higher compression ratio than existing ones.
Diancheng WU
Chinese Academy of Sciences
Yu LIU
Chinese Academy of Sciences
Hao ZHU
Chinese Academy of Sciences
Donghui WANG
Chinese Academy of Sciences
Chengpeng HAO
Chinese Academy of Sciences
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Diancheng WU, Yu LIU, Hao ZHU, Donghui WANG, Chengpeng HAO, "A Novel Pattern Run-Length Coding Method for Test Data Compression" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 9, pp. 1201-1204, September 2013, doi: 10.1587/transele.E96.C.1201.
Abstract: This paper presents a novel data compression method for testing integrated circuits within the framework of pattern run-length coding. The test set is firstly divided into 2n-length patterns where n is a natural number. Then the compatibility of each pattern, which can be an external type, or an internal type, is analyzed. At last, the codeword of each pattern is generated according to its analysis result. Experimental results for large ISCAS89 benchmarks show that the proposed method can obtain a higher compression ratio than existing ones.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.1201/_p
Copy
@ARTICLE{e96-c_9_1201,
author={Diancheng WU, Yu LIU, Hao ZHU, Donghui WANG, Chengpeng HAO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Novel Pattern Run-Length Coding Method for Test Data Compression},
year={2013},
volume={E96-C},
number={9},
pages={1201-1204},
abstract={This paper presents a novel data compression method for testing integrated circuits within the framework of pattern run-length coding. The test set is firstly divided into 2n-length patterns where n is a natural number. Then the compatibility of each pattern, which can be an external type, or an internal type, is analyzed. At last, the codeword of each pattern is generated according to its analysis result. Experimental results for large ISCAS89 benchmarks show that the proposed method can obtain a higher compression ratio than existing ones.},
keywords={},
doi={10.1587/transele.E96.C.1201},
ISSN={1745-1353},
month={September},}
Copy
TY - JOUR
TI - A Novel Pattern Run-Length Coding Method for Test Data Compression
T2 - IEICE TRANSACTIONS on Electronics
SP - 1201
EP - 1204
AU - Diancheng WU
AU - Yu LIU
AU - Hao ZHU
AU - Donghui WANG
AU - Chengpeng HAO
PY - 2013
DO - 10.1587/transele.E96.C.1201
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2013
AB - This paper presents a novel data compression method for testing integrated circuits within the framework of pattern run-length coding. The test set is firstly divided into 2n-length patterns where n is a natural number. Then the compatibility of each pattern, which can be an external type, or an internal type, is analyzed. At last, the codeword of each pattern is generated according to its analysis result. Experimental results for large ISCAS89 benchmarks show that the proposed method can obtain a higher compression ratio than existing ones.
ER -