IEICE TRANSACTIONS on Electronics
A Delay Evaluation Circuit for Analog BIST Function
Summary :
Process variation causes significant fluctuations in the timing performance of analog circuits, which causes a fraction of circuits to fail specifications. By testing the delay-performance, we can recognize the failed circuits during production testing. In this paper, we have proposed a low overhead and process tolerant delay evaluation circuit for built-in self test (BIST) function for analog differential circuits. This circuit contains a delay generation cell, an input differential signal generation cell, a delay matching cell, a sample-hold circuit, and a comparator. This circuit was implemented with 0.18 µm CMOS process. Simulation results over process variation, devices mismatch and layout parasitics, but without silicon measurement, show that the accuracy in delay detection is within 5 ps. A case study was done over a feed-forward equalizer (FFE). A typical use of this circuit is testing the delay of various FIR (Finite Impulse Response) filters.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E96-C No.3 pp.393-401
- Publication Date
- 2013/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E96.C.393
- Type of Manuscript
- PAPER
- Category
- Semiconductor Materials and Devices
Authors
Keyword
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Zhengliang LV, Shiyuan YANG, Hong WANG, Linda MILOR, "A Delay Evaluation Circuit for Analog BIST Function" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 3, pp. 393-401, March 2013, doi: 10.1587/transele.E96.C.393.
Abstract: Process variation causes significant fluctuations in the timing performance of analog circuits, which causes a fraction of circuits to fail specifications. By testing the delay-performance, we can recognize the failed circuits during production testing. In this paper, we have proposed a low overhead and process tolerant delay evaluation circuit for built-in self test (BIST) function for analog differential circuits. This circuit contains a delay generation cell, an input differential signal generation cell, a delay matching cell, a sample-hold circuit, and a comparator. This circuit was implemented with 0.18 µm CMOS process. Simulation results over process variation, devices mismatch and layout parasitics, but without silicon measurement, show that the accuracy in delay detection is within 5 ps. A case study was done over a feed-forward equalizer (FFE). A typical use of this circuit is testing the delay of various FIR (Finite Impulse Response) filters.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.393/_p
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@ARTICLE{e96-c_3_393,
author={Zhengliang LV, Shiyuan YANG, Hong WANG, Linda MILOR, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Delay Evaluation Circuit for Analog BIST Function},
year={2013},
volume={E96-C},
number={3},
pages={393-401},
abstract={Process variation causes significant fluctuations in the timing performance of analog circuits, which causes a fraction of circuits to fail specifications. By testing the delay-performance, we can recognize the failed circuits during production testing. In this paper, we have proposed a low overhead and process tolerant delay evaluation circuit for built-in self test (BIST) function for analog differential circuits. This circuit contains a delay generation cell, an input differential signal generation cell, a delay matching cell, a sample-hold circuit, and a comparator. This circuit was implemented with 0.18 µm CMOS process. Simulation results over process variation, devices mismatch and layout parasitics, but without silicon measurement, show that the accuracy in delay detection is within 5 ps. A case study was done over a feed-forward equalizer (FFE). A typical use of this circuit is testing the delay of various FIR (Finite Impulse Response) filters.},
keywords={},
doi={10.1587/transele.E96.C.393},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - A Delay Evaluation Circuit for Analog BIST Function
T2 - IEICE TRANSACTIONS on Electronics
SP - 393
EP - 401
AU - Zhengliang LV
AU - Shiyuan YANG
AU - Hong WANG
AU - Linda MILOR
PY - 2013
DO - 10.1587/transele.E96.C.393
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2013
AB - Process variation causes significant fluctuations in the timing performance of analog circuits, which causes a fraction of circuits to fail specifications. By testing the delay-performance, we can recognize the failed circuits during production testing. In this paper, we have proposed a low overhead and process tolerant delay evaluation circuit for built-in self test (BIST) function for analog differential circuits. This circuit contains a delay generation cell, an input differential signal generation cell, a delay matching cell, a sample-hold circuit, and a comparator. This circuit was implemented with 0.18 µm CMOS process. Simulation results over process variation, devices mismatch and layout parasitics, but without silicon measurement, show that the accuracy in delay detection is within 5 ps. A case study was done over a feed-forward equalizer (FFE). A typical use of this circuit is testing the delay of various FIR (Finite Impulse Response) filters.
ER -
English
