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Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design
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Power consumption has recently emerged as a first class design constraint in system LSI designs. Specially, leakage power has occupied a large part of the total power consumption. Therefore, reduction of leakage power is indispensable for efficient design of high-performance system LSIs. Since 2006, we have carried out a research project called “Innovative Power Control for Ultra Low-Power and High-Performance System LSIs”, supported by Japan Science and Technology Agency as a CREST research program. One of the major objectives of this project is reducing the leakage power consumption of system LSIs by innovative power control through tight cooperation and co-optimization of circuit technology, architecture, and system software designs. In this project, we focused on power gating as a circuit technique for reducing leakage power. Temporal granularity is one of the most important issue in power gating. Thus, we have developed a series of Geysers as proof-of-concept CPUs which provide several mechanisms of fine-grained run-time power gating. In this paper, we describe their concept and design, and explain why co-optimization of different design layers are important. Then, three kinds of power gating implementations and their evaluation are presented from the view point of power saving and temporal granularity.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E96-C No.4 pp.404-412
- Publication Date
- 2013/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E96.C.404
- Type of Manuscript
- Special Section INVITED PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
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Hiroshi NAKAMURA, Weihan WANG, Yuya OHTA, Kimiyoshi USAMI, Hideharu AMANO, Masaaki KONDO, Mitaro NAMIKI, "Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 4, pp. 404-412, April 2013, doi: 10.1587/transele.E96.C.404.
Abstract: Power consumption has recently emerged as a first class design constraint in system LSI designs. Specially, leakage power has occupied a large part of the total power consumption. Therefore, reduction of leakage power is indispensable for efficient design of high-performance system LSIs. Since 2006, we have carried out a research project called “Innovative Power Control for Ultra Low-Power and High-Performance System LSIs”, supported by Japan Science and Technology Agency as a CREST research program. One of the major objectives of this project is reducing the leakage power consumption of system LSIs by innovative power control through tight cooperation and co-optimization of circuit technology, architecture, and system software designs. In this project, we focused on power gating as a circuit technique for reducing leakage power. Temporal granularity is one of the most important issue in power gating. Thus, we have developed a series of Geysers as proof-of-concept CPUs which provide several mechanisms of fine-grained run-time power gating. In this paper, we describe their concept and design, and explain why co-optimization of different design layers are important. Then, three kinds of power gating implementations and their evaluation are presented from the view point of power saving and temporal granularity.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.404/_p
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@ARTICLE{e96-c_4_404,
author={Hiroshi NAKAMURA, Weihan WANG, Yuya OHTA, Kimiyoshi USAMI, Hideharu AMANO, Masaaki KONDO, Mitaro NAMIKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design},
year={2013},
volume={E96-C},
number={4},
pages={404-412},
abstract={Power consumption has recently emerged as a first class design constraint in system LSI designs. Specially, leakage power has occupied a large part of the total power consumption. Therefore, reduction of leakage power is indispensable for efficient design of high-performance system LSIs. Since 2006, we have carried out a research project called “Innovative Power Control for Ultra Low-Power and High-Performance System LSIs”, supported by Japan Science and Technology Agency as a CREST research program. One of the major objectives of this project is reducing the leakage power consumption of system LSIs by innovative power control through tight cooperation and co-optimization of circuit technology, architecture, and system software designs. In this project, we focused on power gating as a circuit technique for reducing leakage power. Temporal granularity is one of the most important issue in power gating. Thus, we have developed a series of Geysers as proof-of-concept CPUs which provide several mechanisms of fine-grained run-time power gating. In this paper, we describe their concept and design, and explain why co-optimization of different design layers are important. Then, three kinds of power gating implementations and their evaluation are presented from the view point of power saving and temporal granularity.},
keywords={},
doi={10.1587/transele.E96.C.404},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 404
EP - 412
AU - Hiroshi NAKAMURA
AU - Weihan WANG
AU - Yuya OHTA
AU - Kimiyoshi USAMI
AU - Hideharu AMANO
AU - Masaaki KONDO
AU - Mitaro NAMIKI
PY - 2013
DO - 10.1587/transele.E96.C.404
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2013
AB - Power consumption has recently emerged as a first class design constraint in system LSI designs. Specially, leakage power has occupied a large part of the total power consumption. Therefore, reduction of leakage power is indispensable for efficient design of high-performance system LSIs. Since 2006, we have carried out a research project called “Innovative Power Control for Ultra Low-Power and High-Performance System LSIs”, supported by Japan Science and Technology Agency as a CREST research program. One of the major objectives of this project is reducing the leakage power consumption of system LSIs by innovative power control through tight cooperation and co-optimization of circuit technology, architecture, and system software designs. In this project, we focused on power gating as a circuit technique for reducing leakage power. Temporal granularity is one of the most important issue in power gating. Thus, we have developed a series of Geysers as proof-of-concept CPUs which provide several mechanisms of fine-grained run-time power gating. In this paper, we describe their concept and design, and explain why co-optimization of different design layers are important. Then, three kinds of power gating implementations and their evaluation are presented from the view point of power saving and temporal granularity.
ER -
English
