A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops

Toshihiro KONISHI; Keisuke OKUNO; Shintaro IZUMI; Masahiko YOSHIMOTO; Hiroshi KAWAGUCHI

doi:10.1587/transele.E96.C.546

A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops

Toshihiro KONISHI, Keisuke OKUNO, Shintaro IZUMI, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI

Full Text Views

0

Cite this

Summary :

We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 µm² and 281 µW.

Publication: IEICE TRANSACTIONS on Electronics Vol.E96-C No.4 pp.546-552

Publication Date: 2013/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E96.C.546

Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)

Category

Cite this

Copy

Toshihiro KONISHI, Keisuke OKUNO, Shintaro IZUMI, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI, "A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops" in IEICE TRANSACTIONS on Electronics, vol. E96-C, no. 4, pp. 546-552, April 2013, doi: 10.1587/transele.E96.C.546.
Abstract: We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 µm² and 281 µW.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.546/_p

Copy

@ARTICLE{e96-c_4_546,
author={Toshihiro KONISHI, Keisuke OKUNO, Shintaro IZUMI, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops},
year={2013},
volume={E96-C},
number={4},
pages={546-552},
abstract={We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 µm² and 281 µW.},
keywords={},
doi={10.1587/transele.E96.C.546},
ISSN={1745-1353},
month={April},}

Copy

TY - JOUR
TI - A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops
T2 - IEICE TRANSACTIONS on Electronics
SP - 546
EP - 552
AU - Toshihiro KONISHI
AU - Keisuke OKUNO
AU - Shintaro IZUMI
AU - Masahiko YOSHIMOTO
AU - Hiroshi KAWAGUCHI
PY - 2013
DO - 10.1587/transele.E96.C.546
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2013
AB - We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 µm² and 281 µW.
ER -