IEICE TRANSACTIONS on Electronics
High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2:1 Multiplexer and 1:2 Demultiplexer Modules Using 1-µm InP/InGaAs/InP Double Heterojunction Bipolar Transistors
Summary :
We fabricated low-jitter 2:1 multiplexer (MUX) and 1:2 demultiplexer (DEMUX) modules for bit error rate testers that can be used for research into ultra-high-bitrate communication subsystems and devices with bitrates of over 100 Gbit/s. The 1:2 DEMUX IC design took into consideration an IC layout allowing module pin placement for optimal utility. With regard to mounting, the 2:1 MUX and 1:2 DEMUX modules were constructed using transmission lines of grounded coplanar waveguide (G-CPW) configuration, which offers excellent high-frequency characteristics. These modules operated at 113 Gbit/s with a low root mean square jitter of 548 fs and 587 fs, respectively.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E96-C No.6 pp.912-919
- Publication Date
- 2013/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E96.C.912
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
Yutaka ARAYASHIKI
Anritsu Devices
Takashi KAMIZONO
Anritsu Devices
Yukio OHKUBO
Anritsu Devices
Taisuke MATSUMOTO
Anritsu Devices
Yoshiaki AMANO
Anritsu Devices
Yutaka MATSUOKA
Anritsu Devices
Keyword
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Yutaka ARAYASHIKI, Takashi KAMIZONO, Yukio OHKUBO, Taisuke MATSUMOTO, Yoshiaki AMANO, Yutaka MATSUOKA, "High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2:1 Multiplexer and 1:2 Demultiplexer Modules Using 1-µm InP/InGaAs/InP Double Heterojunction Bipolar Transistors" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 6, pp. 912-919, June 2013, doi: 10.1587/transele.E96.C.912.
Abstract: We fabricated low-jitter 2:1 multiplexer (MUX) and 1:2 demultiplexer (DEMUX) modules for bit error rate testers that can be used for research into ultra-high-bitrate communication subsystems and devices with bitrates of over 100 Gbit/s. The 1:2 DEMUX IC design took into consideration an IC layout allowing module pin placement for optimal utility. With regard to mounting, the 2:1 MUX and 1:2 DEMUX modules were constructed using transmission lines of grounded coplanar waveguide (G-CPW) configuration, which offers excellent high-frequency characteristics. These modules operated at 113 Gbit/s with a low root mean square jitter of 548 fs and 587 fs, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.912/_p
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@ARTICLE{e96-c_6_912,
author={Yutaka ARAYASHIKI, Takashi KAMIZONO, Yukio OHKUBO, Taisuke MATSUMOTO, Yoshiaki AMANO, Yutaka MATSUOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2:1 Multiplexer and 1:2 Demultiplexer Modules Using 1-µm InP/InGaAs/InP Double Heterojunction Bipolar Transistors},
year={2013},
volume={E96-C},
number={6},
pages={912-919},
abstract={We fabricated low-jitter 2:1 multiplexer (MUX) and 1:2 demultiplexer (DEMUX) modules for bit error rate testers that can be used for research into ultra-high-bitrate communication subsystems and devices with bitrates of over 100 Gbit/s. The 1:2 DEMUX IC design took into consideration an IC layout allowing module pin placement for optimal utility. With regard to mounting, the 2:1 MUX and 1:2 DEMUX modules were constructed using transmission lines of grounded coplanar waveguide (G-CPW) configuration, which offers excellent high-frequency characteristics. These modules operated at 113 Gbit/s with a low root mean square jitter of 548 fs and 587 fs, respectively.},
keywords={},
doi={10.1587/transele.E96.C.912},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2:1 Multiplexer and 1:2 Demultiplexer Modules Using 1-µm InP/InGaAs/InP Double Heterojunction Bipolar Transistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 912
EP - 919
AU - Yutaka ARAYASHIKI
AU - Takashi KAMIZONO
AU - Yukio OHKUBO
AU - Taisuke MATSUMOTO
AU - Yoshiaki AMANO
AU - Yutaka MATSUOKA
PY - 2013
DO - 10.1587/transele.E96.C.912
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2013
AB - We fabricated low-jitter 2:1 multiplexer (MUX) and 1:2 demultiplexer (DEMUX) modules for bit error rate testers that can be used for research into ultra-high-bitrate communication subsystems and devices with bitrates of over 100 Gbit/s. The 1:2 DEMUX IC design took into consideration an IC layout allowing module pin placement for optimal utility. With regard to mounting, the 2:1 MUX and 1:2 DEMUX modules were constructed using transmission lines of grounded coplanar waveguide (G-CPW) configuration, which offers excellent high-frequency characteristics. These modules operated at 113 Gbit/s with a low root mean square jitter of 548 fs and 587 fs, respectively.
ER -
English
