A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle

Pil-Ho LEE; Hyun Bae LEE; Young-Chan JANG

doi:10.1587/transele.E97.C.463

A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle

Pil-Ho LEE, Hyun Bae LEE, Young-Chan JANG

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A 125MHz 64-phase delay-locked loop (DLL) is implemented for time recovery in a digital wire-line system. The architecture of the proposed DLL comprises a coarse-locking circuit added to a conventional DLL circuit, which consists of a delay line including a bias circuit, phase detector, charge pump, and loop filter. The proposed coarse-locking circuit reduces the locking time of the DLL and prevents harmonic locking, regardless of the duty cycle of the clock. In order to verify the performance of the proposed coarse-locking circuit, a 64-phase DLL with an operating frequency range of 40 to 200MHz is fabricated using a 0.18-µm 1-poly 6-metal CMOS process with a 1.8V supply. The measured rms and peak-to-peak jitter of the output clock are 3.07ps and 21.1ps, respectively. The DNL and INL of the 64-phase output clock are measured to be -0.338/+0.164 LSB and -0.464/+0.171 LSB, respectively, at an operating frequency of 125MHz. The area and power consumption of the implemented DLL are 0.3mm² and 12.7mW, respectively.

Publication: IEICE TRANSACTIONS on Electronics Vol.E97-C No.5 pp.463-467

Publication Date: 2014/05/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E97.C.463

Type of Manuscript: BRIEF PAPER

Category: Integrated Electronics

Authors

Pil-Ho LEE
  Kumoh National Institute of Technology
Hyun Bae LEE
  SK Hynix Semiconductor Inc.
Young-Chan JANG
  Kumoh National Institute of Technology

Keyword

multi-phase DLL, harmonic lock, coarse-locking circuit, initial phase detector, duty cycle

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Pil-Ho LEE, Hyun Bae LEE, Young-Chan JANG, "A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle" in IEICE TRANSACTIONS on Electronics, vol. E97-C, no. 5, pp. 463-467, May 2014, doi: 10.1587/transele.E97.C.463.
Abstract: A 125MHz 64-phase delay-locked loop (DLL) is implemented for time recovery in a digital wire-line system. The architecture of the proposed DLL comprises a coarse-locking circuit added to a conventional DLL circuit, which consists of a delay line including a bias circuit, phase detector, charge pump, and loop filter. The proposed coarse-locking circuit reduces the locking time of the DLL and prevents harmonic locking, regardless of the duty cycle of the clock. In order to verify the performance of the proposed coarse-locking circuit, a 64-phase DLL with an operating frequency range of 40 to 200MHz is fabricated using a 0.18-µm 1-poly 6-metal CMOS process with a 1.8V supply. The measured rms and peak-to-peak jitter of the output clock are 3.07ps and 21.1ps, respectively. The DNL and INL of the 64-phase output clock are measured to be -0.338/+0.164 LSB and -0.464/+0.171 LSB, respectively, at an operating frequency of 125MHz. The area and power consumption of the implemented DLL are 0.3mm² and 12.7mW, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E97.C.463/_p

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@ARTICLE{e97-c_5_463,
author={Pil-Ho LEE, Hyun Bae LEE, Young-Chan JANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle},
year={2014},
volume={E97-C},
number={5},
pages={463-467},
abstract={A 125MHz 64-phase delay-locked loop (DLL) is implemented for time recovery in a digital wire-line system. The architecture of the proposed DLL comprises a coarse-locking circuit added to a conventional DLL circuit, which consists of a delay line including a bias circuit, phase detector, charge pump, and loop filter. The proposed coarse-locking circuit reduces the locking time of the DLL and prevents harmonic locking, regardless of the duty cycle of the clock. In order to verify the performance of the proposed coarse-locking circuit, a 64-phase DLL with an operating frequency range of 40 to 200MHz is fabricated using a 0.18-µm 1-poly 6-metal CMOS process with a 1.8V supply. The measured rms and peak-to-peak jitter of the output clock are 3.07ps and 21.1ps, respectively. The DNL and INL of the 64-phase output clock are measured to be -0.338/+0.164 LSB and -0.464/+0.171 LSB, respectively, at an operating frequency of 125MHz. The area and power consumption of the implemented DLL are 0.3mm² and 12.7mW, respectively.},
keywords={},
doi={10.1587/transele.E97.C.463},
ISSN={1745-1353},
month={May},}

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TY - JOUR
TI - A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle
T2 - IEICE TRANSACTIONS on Electronics
SP - 463
EP - 467
AU - Pil-Ho LEE
AU - Hyun Bae LEE
AU - Young-Chan JANG
PY - 2014
DO - 10.1587/transele.E97.C.463
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E97-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2014
AB - A 125MHz 64-phase delay-locked loop (DLL) is implemented for time recovery in a digital wire-line system. The architecture of the proposed DLL comprises a coarse-locking circuit added to a conventional DLL circuit, which consists of a delay line including a bias circuit, phase detector, charge pump, and loop filter. The proposed coarse-locking circuit reduces the locking time of the DLL and prevents harmonic locking, regardless of the duty cycle of the clock. In order to verify the performance of the proposed coarse-locking circuit, a 64-phase DLL with an operating frequency range of 40 to 200MHz is fabricated using a 0.18-µm 1-poly 6-metal CMOS process with a 1.8V supply. The measured rms and peak-to-peak jitter of the output clock are 3.07ps and 21.1ps, respectively. The DNL and INL of the 64-phase output clock are measured to be -0.338/+0.164 LSB and -0.464/+0.171 LSB, respectively, at an operating frequency of 125MHz. The area and power consumption of the implemented DLL are 0.3mm² and 12.7mW, respectively.
ER -