An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU
Summary :
Electromagnetic field analysis is a time-consuming process, and a method involving the use of an FPGA accelerator is one of the attractive ways to accelerate the analysis; the other method involve the use of CPU and GPU. In this paper, we propose an FPGA accelerator dedicated for a two-dimensional finite-difference time-domain (FDTD) method. This accelerator is based on a two-dimensional single instruction multiple data (SIMD) array architecture. Each processing element (PE) is composed of a six-stage pipeline that is optimized for the FDTD method. Moreover, driving signal generation and impedance termination are also implemented in the hardware. We demonstrate that our accelerator is 11 times faster than existing FPGA accelerators and 9 times faster than parallel computing on the NVIDIA Tesla C2075. As an application of the high-speed FDTD accelerator, the design optimization of a waveguide is shown.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E97-C No.7 pp.697-706
- Publication Date
- 2014/07/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E97.C.697
- Type of Manuscript
- Special Section PAPER (Special Section on Recent Advances in Simulation Techniques and Their Applications for Electronics)
- Category
Authors
Ryota TAKASU
Tokyo University of Agriculture and Technology
Yoichi TOMIOKA
Tokyo University of Agriculture and Technology
Yutaro ISHIGAKI
Tokyo University of Agriculture and Technology
Ning LI
Tokyo University of Agriculture and Technology
Tsugimichi SHIBATA
NTT Microsystem Integration Laboratories
Mamoru NAKANISHI
NTT Microsystem Integration Laboratories
Hitoshi KITAZAWA
Tokyo University of Agriculture and Technology
Keyword
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Ryota TAKASU, Yoichi TOMIOKA, Yutaro ISHIGAKI, Ning LI, Tsugimichi SHIBATA, Mamoru NAKANISHI, Hitoshi KITAZAWA, "An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU" in IEICE TRANSACTIONS on Electronics,
vol. E97-C, no. 7, pp. 697-706, July 2014, doi: 10.1587/transele.E97.C.697.
Abstract: Electromagnetic field analysis is a time-consuming process, and a method involving the use of an FPGA accelerator is one of the attractive ways to accelerate the analysis; the other method involve the use of CPU and GPU. In this paper, we propose an FPGA accelerator dedicated for a two-dimensional finite-difference time-domain (FDTD) method. This accelerator is based on a two-dimensional single instruction multiple data (SIMD) array architecture. Each processing element (PE) is composed of a six-stage pipeline that is optimized for the FDTD method. Moreover, driving signal generation and impedance termination are also implemented in the hardware. We demonstrate that our accelerator is 11 times faster than existing FPGA accelerators and 9 times faster than parallel computing on the NVIDIA Tesla C2075. As an application of the high-speed FDTD accelerator, the design optimization of a waveguide is shown.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E97.C.697/_p
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@ARTICLE{e97-c_7_697,
author={Ryota TAKASU, Yoichi TOMIOKA, Yutaro ISHIGAKI, Ning LI, Tsugimichi SHIBATA, Mamoru NAKANISHI, Hitoshi KITAZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU},
year={2014},
volume={E97-C},
number={7},
pages={697-706},
abstract={Electromagnetic field analysis is a time-consuming process, and a method involving the use of an FPGA accelerator is one of the attractive ways to accelerate the analysis; the other method involve the use of CPU and GPU. In this paper, we propose an FPGA accelerator dedicated for a two-dimensional finite-difference time-domain (FDTD) method. This accelerator is based on a two-dimensional single instruction multiple data (SIMD) array architecture. Each processing element (PE) is composed of a six-stage pipeline that is optimized for the FDTD method. Moreover, driving signal generation and impedance termination are also implemented in the hardware. We demonstrate that our accelerator is 11 times faster than existing FPGA accelerators and 9 times faster than parallel computing on the NVIDIA Tesla C2075. As an application of the high-speed FDTD accelerator, the design optimization of a waveguide is shown.},
keywords={},
doi={10.1587/transele.E97.C.697},
ISSN={1745-1353},
month={July},}
Copy
TY - JOUR
TI - An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU
T2 - IEICE TRANSACTIONS on Electronics
SP - 697
EP - 706
AU - Ryota TAKASU
AU - Yoichi TOMIOKA
AU - Yutaro ISHIGAKI
AU - Ning LI
AU - Tsugimichi SHIBATA
AU - Mamoru NAKANISHI
AU - Hitoshi KITAZAWA
PY - 2014
DO - 10.1587/transele.E97.C.697
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E97-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2014
AB - Electromagnetic field analysis is a time-consuming process, and a method involving the use of an FPGA accelerator is one of the attractive ways to accelerate the analysis; the other method involve the use of CPU and GPU. In this paper, we propose an FPGA accelerator dedicated for a two-dimensional finite-difference time-domain (FDTD) method. This accelerator is based on a two-dimensional single instruction multiple data (SIMD) array architecture. Each processing element (PE) is composed of a six-stage pipeline that is optimized for the FDTD method. Moreover, driving signal generation and impedance termination are also implemented in the hardware. We demonstrate that our accelerator is 11 times faster than existing FPGA accelerators and 9 times faster than parallel computing on the NVIDIA Tesla C2075. As an application of the high-speed FDTD accelerator, the design optimization of a waveguide is shown.
ER -
English
