Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture
Summary :
This paper proposes the proportional static-phase-error reduction (SPER) for the frequency-multiplier-based delay-locked-loop (DLL) architecture. The frequency multiplier (FM) can synthesize a combined clock to solve the high operational frequency of DLL. However, FM is sensitive to the static phase error of DLL. A SPER loop adopts a timing amplifier and a coarse-fine tuning technique to enhance the deterministic jitter of FM. The SPER loop proportionally reduces the static phase error and can extend the operating range of FM.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E99-C No.6 pp.655-658
- Publication Date
- 2016/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E99.C.655
- Type of Manuscript
- BRIEF PAPER
- Category
Authors
Yo-Hao TU
National Central University
Jen-Chieh LIU
National United University
Kuo-Hsing CHENG
National Central University
Keyword
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Yo-Hao TU, Jen-Chieh LIU, Kuo-Hsing CHENG, "Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E99-C, no. 6, pp. 655-658, June 2016, doi: 10.1587/transele.E99.C.655.
Abstract: This paper proposes the proportional static-phase-error reduction (SPER) for the frequency-multiplier-based delay-locked-loop (DLL) architecture. The frequency multiplier (FM) can synthesize a combined clock to solve the high operational frequency of DLL. However, FM is sensitive to the static phase error of DLL. A SPER loop adopts a timing amplifier and a coarse-fine tuning technique to enhance the deterministic jitter of FM. The SPER loop proportionally reduces the static phase error and can extend the operating range of FM.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.655/_p
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@ARTICLE{e99-c_6_655,
author={Yo-Hao TU, Jen-Chieh LIU, Kuo-Hsing CHENG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture},
year={2016},
volume={E99-C},
number={6},
pages={655-658},
abstract={This paper proposes the proportional static-phase-error reduction (SPER) for the frequency-multiplier-based delay-locked-loop (DLL) architecture. The frequency multiplier (FM) can synthesize a combined clock to solve the high operational frequency of DLL. However, FM is sensitive to the static phase error of DLL. A SPER loop adopts a timing amplifier and a coarse-fine tuning technique to enhance the deterministic jitter of FM. The SPER loop proportionally reduces the static phase error and can extend the operating range of FM.},
keywords={},
doi={10.1587/transele.E99.C.655},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 655
EP - 658
AU - Yo-Hao TU
AU - Jen-Chieh LIU
AU - Kuo-Hsing CHENG
PY - 2016
DO - 10.1587/transele.E99.C.655
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2016
AB - This paper proposes the proportional static-phase-error reduction (SPER) for the frequency-multiplier-based delay-locked-loop (DLL) architecture. The frequency multiplier (FM) can synthesize a combined clock to solve the high operational frequency of DLL. However, FM is sensitive to the static phase error of DLL. A SPER loop adopts a timing amplifier and a coarse-fine tuning technique to enhance the deterministic jitter of FM. The SPER loop proportionally reduces the static phase error and can extend the operating range of FM.
ER -
English
