IEICE TRANSACTIONS on Fundamentals
Low-Power Field-Programmable VLSI Using Multiple Supply Voltages
Summary :
A low-power field-programmable VLSI (FPVLSI) is presented to overcome the problem of large power consumption in field-programmable gate arrays (FPGAs). To reduce power consumption in routing networks, the FPVLSI consists of cells that are based on a bit-serial pipeline architecture which reduces routing block complexity. Moreover, a level-converter-less multiple-supply-voltage scheme using dynamic circuits is proposed, where the cells in non-critical paths use a low supply voltage for low power under a speed constraint. The FPVLSI is evaluated based on a 0.18-µm CMOS design rule. The power consumption of the FPVLSI using multiple supply voltages is reduced to 17% or less compared to that of the static-circuit-based FPVLSI using multiple supply voltages.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.12 pp.3298-3305
- Publication Date
- 2005/12/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.12.3298
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Low Power Methodology
Authors
Keyword
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Weisheng CHONG, Masanori HARIYAMA, Michitaka KAMEYAMA, "Low-Power Field-Programmable VLSI Using Multiple Supply Voltages" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 12, pp. 3298-3305, December 2005, doi: 10.1093/ietfec/e88-a.12.3298.
Abstract: A low-power field-programmable VLSI (FPVLSI) is presented to overcome the problem of large power consumption in field-programmable gate arrays (FPGAs). To reduce power consumption in routing networks, the FPVLSI consists of cells that are based on a bit-serial pipeline architecture which reduces routing block complexity. Moreover, a level-converter-less multiple-supply-voltage scheme using dynamic circuits is proposed, where the cells in non-critical paths use a low supply voltage for low power under a speed constraint. The FPVLSI is evaluated based on a 0.18-µm CMOS design rule. The power consumption of the FPVLSI using multiple supply voltages is reduced to 17% or less compared to that of the static-circuit-based FPVLSI using multiple supply voltages.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.12.3298/_p
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@ARTICLE{e88-a_12_3298,
author={Weisheng CHONG, Masanori HARIYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low-Power Field-Programmable VLSI Using Multiple Supply Voltages},
year={2005},
volume={E88-A},
number={12},
pages={3298-3305},
abstract={A low-power field-programmable VLSI (FPVLSI) is presented to overcome the problem of large power consumption in field-programmable gate arrays (FPGAs). To reduce power consumption in routing networks, the FPVLSI consists of cells that are based on a bit-serial pipeline architecture which reduces routing block complexity. Moreover, a level-converter-less multiple-supply-voltage scheme using dynamic circuits is proposed, where the cells in non-critical paths use a low supply voltage for low power under a speed constraint. The FPVLSI is evaluated based on a 0.18-µm CMOS design rule. The power consumption of the FPVLSI using multiple supply voltages is reduced to 17% or less compared to that of the static-circuit-based FPVLSI using multiple supply voltages.},
keywords={},
doi={10.1093/ietfec/e88-a.12.3298},
ISSN={},
month={December},}
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TY - JOUR
TI - Low-Power Field-Programmable VLSI Using Multiple Supply Voltages
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3298
EP - 3305
AU - Weisheng CHONG
AU - Masanori HARIYAMA
AU - Michitaka KAMEYAMA
PY - 2005
DO - 10.1093/ietfec/e88-a.12.3298
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2005
AB - A low-power field-programmable VLSI (FPVLSI) is presented to overcome the problem of large power consumption in field-programmable gate arrays (FPGAs). To reduce power consumption in routing networks, the FPVLSI consists of cells that are based on a bit-serial pipeline architecture which reduces routing block complexity. Moreover, a level-converter-less multiple-supply-voltage scheme using dynamic circuits is proposed, where the cells in non-critical paths use a low supply voltage for low power under a speed constraint. The FPVLSI is evaluated based on a 0.18-µm CMOS design rule. The power consumption of the FPVLSI using multiple supply voltages is reduced to 17% or less compared to that of the static-circuit-based FPVLSI using multiple supply voltages.
ER -
English
