IEICE TRANSACTIONS on Fundamentals
Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches
Summary :
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become an inevitable issue for high-performance microprocessor designs. Since on-chip caches are major contributors of the leakage, a number of researchers have proposed efficient leakage reduction techniques. However, it is still not clear that 1) what kind of algorithm can be considered and 2) how much they have impact on energy and performance. To answer these questions, we explore run-time cache management algorithm, and evaluate the energy-performance efficiency for several alternatives.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.4 pp.862-868
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.4.862
- Type of Manuscript
- Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- Category
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Reiko KOMIYA, Koji INOUE, Vasily G. MOSHNYAGA, Kazuaki MURAKAMI, "Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 4, pp. 862-868, April 2005, doi: 10.1093/ietfec/e88-a.4.862.
Abstract: As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become an inevitable issue for high-performance microprocessor designs. Since on-chip caches are major contributors of the leakage, a number of researchers have proposed efficient leakage reduction techniques. However, it is still not clear that 1) what kind of algorithm can be considered and 2) how much they have impact on energy and performance. To answer these questions, we explore run-time cache management algorithm, and evaluate the energy-performance efficiency for several alternatives.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.4.862/_p
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@ARTICLE{e88-a_4_862,
author={Reiko KOMIYA, Koji INOUE, Vasily G. MOSHNYAGA, Kazuaki MURAKAMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches},
year={2005},
volume={E88-A},
number={4},
pages={862-868},
abstract={As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become an inevitable issue for high-performance microprocessor designs. Since on-chip caches are major contributors of the leakage, a number of researchers have proposed efficient leakage reduction techniques. However, it is still not clear that 1) what kind of algorithm can be considered and 2) how much they have impact on energy and performance. To answer these questions, we explore run-time cache management algorithm, and evaluate the energy-performance efficiency for several alternatives.},
keywords={},
doi={10.1093/ietfec/e88-a.4.862},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 862
EP - 868
AU - Reiko KOMIYA
AU - Koji INOUE
AU - Vasily G. MOSHNYAGA
AU - Kazuaki MURAKAMI
PY - 2005
DO - 10.1093/ietfec/e88-a.4.862
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2005
AB - As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become an inevitable issue for high-performance microprocessor designs. Since on-chip caches are major contributors of the leakage, a number of researchers have proposed efficient leakage reduction techniques. However, it is still not clear that 1) what kind of algorithm can be considered and 2) how much they have impact on energy and performance. To answer these questions, we explore run-time cache management algorithm, and evaluate the energy-performance efficiency for several alternatives.
ER -
English
