IEICE TRANSACTIONS on Fundamentals
Design Method for 2-Channel Signal Word Decomposed Filters with Minimum Output Error and Their Effective VLSI Implementation
Summary :
This paper proposes hardware-efficient VLSI architectures for 2-channel signal word decomposed filters (2-ch SWDFs) and their design method in consideration of the implemented circuit size. By consideration of the circuit size in design method, 2-ch SWDFs with a minimum output error among SWDFs whose size is equal to or smaller than a specification can be designed. Canonical Signed Digit expressions are used to effectively represent the filter coefficients of the SWDFs in order to make its circuit size small. Through precise analysis of the internal structures, circuit size can be accurately estimated. Some design examples show that the proposed method can design filters whose output error is about -12 dB lower than that of the linear FIR filters. Compared to an exhaustive search method, our method is much faster and can design filters whose output errors are only about 2 dB more.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.8 pp.2044-2054
- Publication Date
- 2005/08/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.8.2044
- Type of Manuscript
- Special Section PAPER (Special Section on Papers Selected from the 19th Symposium on Signal Processing)
- Category
- Digital Signal Processing
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Kouhei HOSOKAWA, Mitsuhiko YAGYU, Akinori NISHIHARA, "Design Method for 2-Channel Signal Word Decomposed Filters with Minimum Output Error and Their Effective VLSI Implementation" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 8, pp. 2044-2054, August 2005, doi: 10.1093/ietfec/e88-a.8.2044.
Abstract: This paper proposes hardware-efficient VLSI architectures for 2-channel signal word decomposed filters (2-ch SWDFs) and their design method in consideration of the implemented circuit size. By consideration of the circuit size in design method, 2-ch SWDFs with a minimum output error among SWDFs whose size is equal to or smaller than a specification can be designed. Canonical Signed Digit expressions are used to effectively represent the filter coefficients of the SWDFs in order to make its circuit size small. Through precise analysis of the internal structures, circuit size can be accurately estimated. Some design examples show that the proposed method can design filters whose output error is about -12 dB lower than that of the linear FIR filters. Compared to an exhaustive search method, our method is much faster and can design filters whose output errors are only about 2 dB more.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.8.2044/_p
Copy
@ARTICLE{e88-a_8_2044,
author={Kouhei HOSOKAWA, Mitsuhiko YAGYU, Akinori NISHIHARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design Method for 2-Channel Signal Word Decomposed Filters with Minimum Output Error and Their Effective VLSI Implementation},
year={2005},
volume={E88-A},
number={8},
pages={2044-2054},
abstract={This paper proposes hardware-efficient VLSI architectures for 2-channel signal word decomposed filters (2-ch SWDFs) and their design method in consideration of the implemented circuit size. By consideration of the circuit size in design method, 2-ch SWDFs with a minimum output error among SWDFs whose size is equal to or smaller than a specification can be designed. Canonical Signed Digit expressions are used to effectively represent the filter coefficients of the SWDFs in order to make its circuit size small. Through precise analysis of the internal structures, circuit size can be accurately estimated. Some design examples show that the proposed method can design filters whose output error is about -12 dB lower than that of the linear FIR filters. Compared to an exhaustive search method, our method is much faster and can design filters whose output errors are only about 2 dB more.},
keywords={},
doi={10.1093/ietfec/e88-a.8.2044},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - Design Method for 2-Channel Signal Word Decomposed Filters with Minimum Output Error and Their Effective VLSI Implementation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2044
EP - 2054
AU - Kouhei HOSOKAWA
AU - Mitsuhiko YAGYU
AU - Akinori NISHIHARA
PY - 2005
DO - 10.1093/ietfec/e88-a.8.2044
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2005
AB - This paper proposes hardware-efficient VLSI architectures for 2-channel signal word decomposed filters (2-ch SWDFs) and their design method in consideration of the implemented circuit size. By consideration of the circuit size in design method, 2-ch SWDFs with a minimum output error among SWDFs whose size is equal to or smaller than a specification can be designed. Canonical Signed Digit expressions are used to effectively represent the filter coefficients of the SWDFs in order to make its circuit size small. Through precise analysis of the internal structures, circuit size can be accurately estimated. Some design examples show that the proposed method can design filters whose output error is about -12 dB lower than that of the linear FIR filters. Compared to an exhaustive search method, our method is much faster and can design filters whose output errors are only about 2 dB more.
ER -
English
