IEICE TRANSACTIONS on Fundamentals
Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs
Summary :
This paper presents a novel power estimation method for large and complex LSIs. The proposed method is based on simulation and is used for analyzing the ways in chip-scale gate-level circuits including processors and memory are affected by gated-clock power reduction and the voltage drop due to electrical resistance. The chip-scale power estimation based on simulation patterns generally takes enormous time. In order to reduce the time to obtain accurate estimation results based on simulation patterns, we introduce three approaches: "partitioning of target LSIs and simulation pattern," "memory modeling," and "processor modeling." After placing and routing, the target LSIs are partitioned into hierarchical blocks, memory, and processors. The power consumption of each hierarchical block is calculated by using the partitioned patterns generated from chip-scale simulation patterns. The power consumption of the processor and memory blocks is estimated by a method considering the static power consumption and the rate of LSI activity ratio. Experimental results for a commercial 0.18 µm-technology media processing chip show that the proposed method is 23 times faster than the conventional method without partitioning and that both the results are almost the same.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.12 pp.3458-3463
- Publication Date
- 2006/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.12.3458
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Simulation and Verification
Authors
Keyword
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Yuichi NAKAMURA, Takeshi YOSHIMURA, "Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 12, pp. 3458-3463, December 2006, doi: 10.1093/ietfec/e89-a.12.3458.
Abstract: This paper presents a novel power estimation method for large and complex LSIs. The proposed method is based on simulation and is used for analyzing the ways in chip-scale gate-level circuits including processors and memory are affected by gated-clock power reduction and the voltage drop due to electrical resistance. The chip-scale power estimation based on simulation patterns generally takes enormous time. In order to reduce the time to obtain accurate estimation results based on simulation patterns, we introduce three approaches: "partitioning of target LSIs and simulation pattern," "memory modeling," and "processor modeling." After placing and routing, the target LSIs are partitioned into hierarchical blocks, memory, and processors. The power consumption of each hierarchical block is calculated by using the partitioned patterns generated from chip-scale simulation patterns. The power consumption of the processor and memory blocks is estimated by a method considering the static power consumption and the rate of LSI activity ratio. Experimental results for a commercial 0.18 µm-technology media processing chip show that the proposed method is 23 times faster than the conventional method without partitioning and that both the results are almost the same.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.12.3458/_p
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@ARTICLE{e89-a_12_3458,
author={Yuichi NAKAMURA, Takeshi YOSHIMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs},
year={2006},
volume={E89-A},
number={12},
pages={3458-3463},
abstract={This paper presents a novel power estimation method for large and complex LSIs. The proposed method is based on simulation and is used for analyzing the ways in chip-scale gate-level circuits including processors and memory are affected by gated-clock power reduction and the voltage drop due to electrical resistance. The chip-scale power estimation based on simulation patterns generally takes enormous time. In order to reduce the time to obtain accurate estimation results based on simulation patterns, we introduce three approaches: "partitioning of target LSIs and simulation pattern," "memory modeling," and "processor modeling." After placing and routing, the target LSIs are partitioned into hierarchical blocks, memory, and processors. The power consumption of each hierarchical block is calculated by using the partitioned patterns generated from chip-scale simulation patterns. The power consumption of the processor and memory blocks is estimated by a method considering the static power consumption and the rate of LSI activity ratio. Experimental results for a commercial 0.18 µm-technology media processing chip show that the proposed method is 23 times faster than the conventional method without partitioning and that both the results are almost the same.},
keywords={},
doi={10.1093/ietfec/e89-a.12.3458},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3458
EP - 3463
AU - Yuichi NAKAMURA
AU - Takeshi YOSHIMURA
PY - 2006
DO - 10.1093/ietfec/e89-a.12.3458
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2006
AB - This paper presents a novel power estimation method for large and complex LSIs. The proposed method is based on simulation and is used for analyzing the ways in chip-scale gate-level circuits including processors and memory are affected by gated-clock power reduction and the voltage drop due to electrical resistance. The chip-scale power estimation based on simulation patterns generally takes enormous time. In order to reduce the time to obtain accurate estimation results based on simulation patterns, we introduce three approaches: "partitioning of target LSIs and simulation pattern," "memory modeling," and "processor modeling." After placing and routing, the target LSIs are partitioned into hierarchical blocks, memory, and processors. The power consumption of each hierarchical block is calculated by using the partitioned patterns generated from chip-scale simulation patterns. The power consumption of the processor and memory blocks is estimated by a method considering the static power consumption and the rate of LSI activity ratio. Experimental results for a commercial 0.18 µm-technology media processing chip show that the proposed method is 23 times faster than the conventional method without partitioning and that both the results are almost the same.
ER -
English
