IEICE TRANSACTIONS on Fundamentals
A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization
Summary :
A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 µm 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.12 pp.3594-3601
- Publication Date
- 2006/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.12.3594
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- VLSI Architecture
Authors
Keyword
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Yang SONG, Zhenyu LIU, Takeshi IKENAGA, Satoshi GOTO, "A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 12, pp. 3594-3601, December 2006, doi: 10.1093/ietfec/e89-a.12.3594.
Abstract: A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 µm 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.12.3594/_p
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@ARTICLE{e89-a_12_3594,
author={Yang SONG, Zhenyu LIU, Takeshi IKENAGA, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization},
year={2006},
volume={E89-A},
number={12},
pages={3594-3601},
abstract={A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 µm 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25
keywords={},
doi={10.1093/ietfec/e89-a.12.3594},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3594
EP - 3601
AU - Yang SONG
AU - Zhenyu LIU
AU - Takeshi IKENAGA
AU - Satoshi GOTO
PY - 2006
DO - 10.1093/ietfec/e89-a.12.3594
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2006
AB - A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 µm 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25
ER -
English
