A Parallel-In Folding Technique for High-Order FIR Filter Implementation

Lan-Rong DUNG; Hsueh-Chih YANG

doi:10.1093/ietfec/e89-a.12.3659

A Parallel-In Folding Technique for High-Order FIR Filter Implementation

Lan-Rong DUNG, Hsueh-Chih YANG

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This paper presents a hardware-efficient folding technique for high-order FIR filtering while considering the tradeoff between the number of processing elements and throughput rate. Given the throughput rate, one can always employ the minimum number of processing elements for saving the implementation cost and figure out a folded architecture. However, applying inefficient folding techniques may result in costly switches and registers. Therefore, our work intends to evaluate the efficiency for folding techniques in terms of the number of registers, and the power dissipation of registers. As shown in the estimation results, while comparing with the published folded architectures under the same throughput rate, the proposed folding technique can turn out less power dissipation and low hardware complexity than the others. The proposed design has been implemented using TSMC 0.18 µm 1P6M technology. As seen in the post-layout simulation, our design can meet the requirement of IS-95 WCDMA pulse shaping FIR filter while the power consumption can be as low as 16.66 mW.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.12 pp.3659-3665

Publication Date: 2006/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e89-a.12.3659

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: VLSI Architecture

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Lan-Rong DUNG, Hsueh-Chih YANG, "A Parallel-In Folding Technique for High-Order FIR Filter Implementation" in IEICE TRANSACTIONS on Fundamentals, vol. E89-A, no. 12, pp. 3659-3665, December 2006, doi: 10.1093/ietfec/e89-a.12.3659.
Abstract: This paper presents a hardware-efficient folding technique for high-order FIR filtering while considering the tradeoff between the number of processing elements and throughput rate. Given the throughput rate, one can always employ the minimum number of processing elements for saving the implementation cost and figure out a folded architecture. However, applying inefficient folding techniques may result in costly switches and registers. Therefore, our work intends to evaluate the efficiency for folding techniques in terms of the number of registers, and the power dissipation of registers. As shown in the estimation results, while comparing with the published folded architectures under the same throughput rate, the proposed folding technique can turn out less power dissipation and low hardware complexity than the others. The proposed design has been implemented using TSMC 0.18 µm 1P6M technology. As seen in the post-layout simulation, our design can meet the requirement of IS-95 WCDMA pulse shaping FIR filter while the power consumption can be as low as 16.66 mW.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.12.3659/_p

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@ARTICLE{e89-a_12_3659,
author={Lan-Rong DUNG, Hsueh-Chih YANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Parallel-In Folding Technique for High-Order FIR Filter Implementation},
year={2006},
volume={E89-A},
number={12},
pages={3659-3665},
abstract={This paper presents a hardware-efficient folding technique for high-order FIR filtering while considering the tradeoff between the number of processing elements and throughput rate. Given the throughput rate, one can always employ the minimum number of processing elements for saving the implementation cost and figure out a folded architecture. However, applying inefficient folding techniques may result in costly switches and registers. Therefore, our work intends to evaluate the efficiency for folding techniques in terms of the number of registers, and the power dissipation of registers. As shown in the estimation results, while comparing with the published folded architectures under the same throughput rate, the proposed folding technique can turn out less power dissipation and low hardware complexity than the others. The proposed design has been implemented using TSMC 0.18 µm 1P6M technology. As seen in the post-layout simulation, our design can meet the requirement of IS-95 WCDMA pulse shaping FIR filter while the power consumption can be as low as 16.66 mW.},
keywords={},
doi={10.1093/ietfec/e89-a.12.3659},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - A Parallel-In Folding Technique for High-Order FIR Filter Implementation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3659
EP - 3665
AU - Lan-Rong DUNG
AU - Hsueh-Chih YANG
PY - 2006
DO - 10.1093/ietfec/e89-a.12.3659
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2006
AB - This paper presents a hardware-efficient folding technique for high-order FIR filtering while considering the tradeoff between the number of processing elements and throughput rate. Given the throughput rate, one can always employ the minimum number of processing elements for saving the implementation cost and figure out a folded architecture. However, applying inefficient folding techniques may result in costly switches and registers. Therefore, our work intends to evaluate the efficiency for folding techniques in terms of the number of registers, and the power dissipation of registers. As shown in the estimation results, while comparing with the published folded architectures under the same throughput rate, the proposed folding technique can turn out less power dissipation and low hardware complexity than the others. The proposed design has been implemented using TSMC 0.18 µm 1P6M technology. As seen in the post-layout simulation, our design can meet the requirement of IS-95 WCDMA pulse shaping FIR filter while the power consumption can be as low as 16.66 mW.
ER -