Modern digital systems design requires us to explore a large and complex design space to find a best configuration which satisfies design requirements. Such exploration requires a sound representation of design space from which design candidates are efficiently generated, each of which then is evaluated. This paper proposes a plan-generation-evaluation framework which supports a complete process of such design space exploration. The plan phase constitutes a design space of all possible design alternatives by means of a formally defined representation scheme of attributed AND-OR graph. The generation phase generates a set of candidates by algorithmic pruning of the design space in an attributed AND-OR graph with respect to design requirements as well as architectural constraints. Finally, the evaluation phase measures performance of design candidates in a pruned graph to select a best one. A complete process of cache design is exemplified to show the effectiveness of the proposed framework.
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Jun Kyoung KIM, Tag Gon KIM, "A Plan-Generation-Evaluation Framework for Design Space Exploration of Digital Systems Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 3, pp. 772-781, March 2006, doi: 10.1093/ietfec/e89-a.3.772.
Abstract: Modern digital systems design requires us to explore a large and complex design space to find a best configuration which satisfies design requirements. Such exploration requires a sound representation of design space from which design candidates are efficiently generated, each of which then is evaluated. This paper proposes a plan-generation-evaluation framework which supports a complete process of such design space exploration. The plan phase constitutes a design space of all possible design alternatives by means of a formally defined representation scheme of attributed AND-OR graph. The generation phase generates a set of candidates by algorithmic pruning of the design space in an attributed AND-OR graph with respect to design requirements as well as architectural constraints. Finally, the evaluation phase measures performance of design candidates in a pruned graph to select a best one. A complete process of cache design is exemplified to show the effectiveness of the proposed framework.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.3.772/_p
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@ARTICLE{e89-a_3_772,
author={Jun Kyoung KIM, Tag Gon KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Plan-Generation-Evaluation Framework for Design Space Exploration of Digital Systems Design},
year={2006},
volume={E89-A},
number={3},
pages={772-781},
abstract={Modern digital systems design requires us to explore a large and complex design space to find a best configuration which satisfies design requirements. Such exploration requires a sound representation of design space from which design candidates are efficiently generated, each of which then is evaluated. This paper proposes a plan-generation-evaluation framework which supports a complete process of such design space exploration. The plan phase constitutes a design space of all possible design alternatives by means of a formally defined representation scheme of attributed AND-OR graph. The generation phase generates a set of candidates by algorithmic pruning of the design space in an attributed AND-OR graph with respect to design requirements as well as architectural constraints. Finally, the evaluation phase measures performance of design candidates in a pruned graph to select a best one. A complete process of cache design is exemplified to show the effectiveness of the proposed framework.},
keywords={},
doi={10.1093/ietfec/e89-a.3.772},
ISSN={1745-1337},
month={March},}
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TY - JOUR
TI - A Plan-Generation-Evaluation Framework for Design Space Exploration of Digital Systems Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 772
EP - 781
AU - Jun Kyoung KIM
AU - Tag Gon KIM
PY - 2006
DO - 10.1093/ietfec/e89-a.3.772
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2006
AB - Modern digital systems design requires us to explore a large and complex design space to find a best configuration which satisfies design requirements. Such exploration requires a sound representation of design space from which design candidates are efficiently generated, each of which then is evaluated. This paper proposes a plan-generation-evaluation framework which supports a complete process of such design space exploration. The plan phase constitutes a design space of all possible design alternatives by means of a formally defined representation scheme of attributed AND-OR graph. The generation phase generates a set of candidates by algorithmic pruning of the design space in an attributed AND-OR graph with respect to design requirements as well as architectural constraints. Finally, the evaluation phase measures performance of design candidates in a pruned graph to select a best one. A complete process of cache design is exemplified to show the effectiveness of the proposed framework.
ER -