IEICE TRANSACTIONS on Fundamentals
Coding Floorplans with Fewer Bits
Summary :
A naive coding of floorplans needs 2m bits for each floorplan. In this paper we give a new simple coding of floorplans, which needs only 5m/3 bits for each floorplan.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.5 pp.1181-1185
- Publication Date
- 2006/05/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.5.1181
- Type of Manuscript
- Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
- Category
Authors
Keyword
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Katsuhisa YAMANAKA, Shin-ichi NAKANO, "Coding Floorplans with Fewer Bits" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 5, pp. 1181-1185, May 2006, doi: 10.1093/ietfec/e89-a.5.1181.
Abstract: A naive coding of floorplans needs 2m bits for each floorplan. In this paper we give a new simple coding of floorplans, which needs only 5m/3 bits for each floorplan.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.5.1181/_p
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@ARTICLE{e89-a_5_1181,
author={Katsuhisa YAMANAKA, Shin-ichi NAKANO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Coding Floorplans with Fewer Bits},
year={2006},
volume={E89-A},
number={5},
pages={1181-1185},
abstract={A naive coding of floorplans needs 2m bits for each floorplan. In this paper we give a new simple coding of floorplans, which needs only 5m/3 bits for each floorplan.},
keywords={},
doi={10.1093/ietfec/e89-a.5.1181},
ISSN={1745-1337},
month={May},}
Copy
TY - JOUR
TI - Coding Floorplans with Fewer Bits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1181
EP - 1185
AU - Katsuhisa YAMANAKA
AU - Shin-ichi NAKANO
PY - 2006
DO - 10.1093/ietfec/e89-a.5.1181
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2006
AB - A naive coding of floorplans needs 2m bits for each floorplan. In this paper we give a new simple coding of floorplans, which needs only 5m/3 bits for each floorplan.
ER -
English
