An Efficient Architecture of High-Performance Deblocking Filter for H.264/AVC

Seonyoung LEE; Kyeongsoon CHO

doi:10.1093/ietfec/e89-a.6.1736

An Efficient Architecture of High-Performance Deblocking Filter for H.264/AVC

Seonyoung LEE, Kyeongsoon CHO

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We devised an efficient architecture of deblocking filter and implemented the circuit with 15,400 logic gates and a 16032 dual-port SRAM using 0.25 µm standard cell technology. This circuit can process 88 image frames with 1,280720 pixels per second at 166 MHz. Our circuit requires smaller number of accesses to the external memory than other approaches and hence causes less bus traffic in the SoC design platform.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.6 pp.1736-1739

Publication Date: 2006/06/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e89-a.6.1736

Type of Manuscript: Special Section LETTER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))

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Seonyoung LEE, Kyeongsoon CHO, "An Efficient Architecture of High-Performance Deblocking Filter for H.264/AVC" in IEICE TRANSACTIONS on Fundamentals, vol. E89-A, no. 6, pp. 1736-1739, June 2006, doi: 10.1093/ietfec/e89-a.6.1736.
Abstract: We devised an efficient architecture of deblocking filter and implemented the circuit with 15,400 logic gates and a 16032 dual-port SRAM using 0.25 µm standard cell technology. This circuit can process 88 image frames with 1,280720 pixels per second at 166 MHz. Our circuit requires smaller number of accesses to the external memory than other approaches and hence causes less bus traffic in the SoC design platform.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.6.1736/_p

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@ARTICLE{e89-a_6_1736,
author={Seonyoung LEE, Kyeongsoon CHO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Efficient Architecture of High-Performance Deblocking Filter for H.264/AVC},
year={2006},
volume={E89-A},
number={6},
pages={1736-1739},
abstract={We devised an efficient architecture of deblocking filter and implemented the circuit with 15,400 logic gates and a 16032 dual-port SRAM using 0.25 µm standard cell technology. This circuit can process 88 image frames with 1,280720 pixels per second at 166 MHz. Our circuit requires smaller number of accesses to the external memory than other approaches and hence causes less bus traffic in the SoC design platform.},
keywords={},
doi={10.1093/ietfec/e89-a.6.1736},
ISSN={1745-1337},
month={June},}

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TY - JOUR
TI - An Efficient Architecture of High-Performance Deblocking Filter for H.264/AVC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1736
EP - 1739
AU - Seonyoung LEE
AU - Kyeongsoon CHO
PY - 2006
DO - 10.1093/ietfec/e89-a.6.1736
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2006
AB - We devised an efficient architecture of deblocking filter and implemented the circuit with 15,400 logic gates and a 16032 dual-port SRAM using 0.25 µm standard cell technology. This circuit can process 88 image frames with 1,280720 pixels per second at 166 MHz. Our circuit requires smaller number of accesses to the external memory than other approaches and hence causes less bus traffic in the SoC design platform.
ER -