Hardware Architecture for Fast Motion Estimation in H.264/AVC Video Coding

Myung-Suk BYEON; Yil-Mi SHIN; Yong-Beom CHO

doi:10.1093/ietfec/e89-a.6.1744

Hardware Architecture for Fast Motion Estimation in H.264/AVC Video Coding

Myung-Suk BYEON, Yil-Mi SHIN, Yong-Beom CHO

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This paper describes the efficiency of VLSI architecture for UMHexagonS (hybrid Unsymmetrical cross Multi Hexagon grid Search) matching algorithm. This algorithm is used for ME (Motion Estimation) of H.264/AVC video compression standard. The UMHexagonS is called a hybrid algorithm since it uses different kinds of searching patterns. VLSI architecture based on UMHexagonS is designed to provide a good tradeoff between gate sizes and high throughput. We implemented this architecture with about 309 K gates and 1/1792 throughput [block/cycle] for a search range of 16 and 44 macro blocks using synthesizable Verilog HDL.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.6 pp.1744-1745

Publication Date: 2006/06/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e89-a.6.1744

Type of Manuscript: Special Section LETTER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))

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Myung-Suk BYEON, Yil-Mi SHIN, Yong-Beom CHO, "Hardware Architecture for Fast Motion Estimation in H.264/AVC Video Coding" in IEICE TRANSACTIONS on Fundamentals, vol. E89-A, no. 6, pp. 1744-1745, June 2006, doi: 10.1093/ietfec/e89-a.6.1744.
Abstract: This paper describes the efficiency of VLSI architecture for UMHexagonS (hybrid Unsymmetrical cross Multi Hexagon grid Search) matching algorithm. This algorithm is used for ME (Motion Estimation) of H.264/AVC video compression standard. The UMHexagonS is called a hybrid algorithm since it uses different kinds of searching patterns. VLSI architecture based on UMHexagonS is designed to provide a good tradeoff between gate sizes and high throughput. We implemented this architecture with about 309 K gates and 1/1792 throughput [block/cycle] for a search range of 16 and 44 macro blocks using synthesizable Verilog HDL.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.6.1744/_p

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@ARTICLE{e89-a_6_1744,
author={Myung-Suk BYEON, Yil-Mi SHIN, Yong-Beom CHO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hardware Architecture for Fast Motion Estimation in H.264/AVC Video Coding},
year={2006},
volume={E89-A},
number={6},
pages={1744-1745},
abstract={This paper describes the efficiency of VLSI architecture for UMHexagonS (hybrid Unsymmetrical cross Multi Hexagon grid Search) matching algorithm. This algorithm is used for ME (Motion Estimation) of H.264/AVC video compression standard. The UMHexagonS is called a hybrid algorithm since it uses different kinds of searching patterns. VLSI architecture based on UMHexagonS is designed to provide a good tradeoff between gate sizes and high throughput. We implemented this architecture with about 309 K gates and 1/1792 throughput [block/cycle] for a search range of 16 and 44 macro blocks using synthesizable Verilog HDL.},
keywords={},
doi={10.1093/ietfec/e89-a.6.1744},
ISSN={1745-1337},
month={June},}

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TY - JOUR
TI - Hardware Architecture for Fast Motion Estimation in H.264/AVC Video Coding
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1744
EP - 1745
AU - Myung-Suk BYEON
AU - Yil-Mi SHIN
AU - Yong-Beom CHO
PY - 2006
DO - 10.1093/ietfec/e89-a.6.1744
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2006
AB - This paper describes the efficiency of VLSI architecture for UMHexagonS (hybrid Unsymmetrical cross Multi Hexagon grid Search) matching algorithm. This algorithm is used for ME (Motion Estimation) of H.264/AVC video compression standard. The UMHexagonS is called a hybrid algorithm since it uses different kinds of searching patterns. VLSI architecture based on UMHexagonS is designed to provide a good tradeoff between gate sizes and high throughput. We implemented this architecture with about 309 K gates and 1/1792 throughput [block/cycle] for a search range of 16 and 44 macro blocks using synthesizable Verilog HDL.
ER -