IEICE TRANSACTIONS on Fundamentals
Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements
Summary :
A new algorithm is proposed to reduce the area of a pipelined circuit using a combination of multi-clock cycle paths, clock scheduling and delay balancing. The algorithm analyzes the circuit and replaces intermediate registers with delay elements under the condition that the circuit works correctly at given target clock-period range with the smaller area. Experiments with pipelined multipliers verify that the proposed algorithm can reduce the area of a pipelined circuit without degrading performance.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.12 pp.2736-2742
- Publication Date
- 2007/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e90-a.12.2736
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Circuit Synthesis
Authors
Keyword
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Bakhtiar Affendi ROSDI, Atsushi TAKAHASHI, "Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements" in IEICE TRANSACTIONS on Fundamentals,
vol. E90-A, no. 12, pp. 2736-2742, December 2007, doi: 10.1093/ietfec/e90-a.12.2736.
Abstract: A new algorithm is proposed to reduce the area of a pipelined circuit using a combination of multi-clock cycle paths, clock scheduling and delay balancing. The algorithm analyzes the circuit and replaces intermediate registers with delay elements under the condition that the circuit works correctly at given target clock-period range with the smaller area. Experiments with pipelined multipliers verify that the proposed algorithm can reduce the area of a pipelined circuit without degrading performance.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.12.2736/_p
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@ARTICLE{e90-a_12_2736,
author={Bakhtiar Affendi ROSDI, Atsushi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements},
year={2007},
volume={E90-A},
number={12},
pages={2736-2742},
abstract={A new algorithm is proposed to reduce the area of a pipelined circuit using a combination of multi-clock cycle paths, clock scheduling and delay balancing. The algorithm analyzes the circuit and replaces intermediate registers with delay elements under the condition that the circuit works correctly at given target clock-period range with the smaller area. Experiments with pipelined multipliers verify that the proposed algorithm can reduce the area of a pipelined circuit without degrading performance.},
keywords={},
doi={10.1093/ietfec/e90-a.12.2736},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2736
EP - 2742
AU - Bakhtiar Affendi ROSDI
AU - Atsushi TAKAHASHI
PY - 2007
DO - 10.1093/ietfec/e90-a.12.2736
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2007
AB - A new algorithm is proposed to reduce the area of a pipelined circuit using a combination of multi-clock cycle paths, clock scheduling and delay balancing. The algorithm analyzes the circuit and replaces intermediate registers with delay elements under the condition that the circuit works correctly at given target clock-period range with the smaller area. Experiments with pipelined multipliers verify that the proposed algorithm can reduce the area of a pipelined circuit without degrading performance.
ER -
English
