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IEICE TRANSACTIONS on Fundamentals

Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints

Hiroaki KOZAWA, Kiyoharu HAMAGUCHI, Toshinobu KASHIWABARA

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Summary :

For formal verification of large-scale digital circuits, a method using satisfiability checking of logic with equality and uninterpreted functions has been proposed. This logic, however, does not consider specific properties of functions or predicates at all, e.g. associative property of addition. In order to ease this problem, we introduce "equivalence constraint" that is a set of formulas representing the properties of functions and predicates, and check the satisfiability of formulas under the constraint. In this report, we show an algorithm for checking satisfiability with equivalence constraint and also experimental results.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.12 pp.2778-2789
Publication Date
2007/12/01
Publicized
Online ISSN
1745-1337
DOI
10.1093/ietfec/e90-a.12.2778
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category
Logic Synthesis and Verification

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