Adaptive Low-Error Fixed-Width Booth Multipliers
Summary :
In this paper, we propose two 2's-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best error-compensation bias in designing a multiplier suitable for VLSI implementation. Last but not least, we show the superior capability of our designs by inscribing it in a speech signal processor. Simulation results indicate that this novel design surpasses the previous fixed-width Booth multiplier in the precision of the product. An average error reduction of 65-84% compared with a direct-truncation fixed-width multiplier is achieved by adding only a few logic gates.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.6 pp.1180-1187
- Publication Date
- 2007/06/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e90-a.6.1180
- Type of Manuscript
- PAPER
- Category
- Circuit Theory
Authors
Keyword
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Min-An SONG, Lan-Da VAN, Sy-Yen KUO, "Adaptive Low-Error Fixed-Width Booth Multipliers" in IEICE TRANSACTIONS on Fundamentals,
vol. E90-A, no. 6, pp. 1180-1187, June 2007, doi: 10.1093/ietfec/e90-a.6.1180.
Abstract: In this paper, we propose two 2's-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best error-compensation bias in designing a multiplier suitable for VLSI implementation. Last but not least, we show the superior capability of our designs by inscribing it in a speech signal processor. Simulation results indicate that this novel design surpasses the previous fixed-width Booth multiplier in the precision of the product. An average error reduction of 65-84% compared with a direct-truncation fixed-width multiplier is achieved by adding only a few logic gates.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.6.1180/_p
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@ARTICLE{e90-a_6_1180,
author={Min-An SONG, Lan-Da VAN, Sy-Yen KUO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Adaptive Low-Error Fixed-Width Booth Multipliers},
year={2007},
volume={E90-A},
number={6},
pages={1180-1187},
abstract={In this paper, we propose two 2's-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best error-compensation bias in designing a multiplier suitable for VLSI implementation. Last but not least, we show the superior capability of our designs by inscribing it in a speech signal processor. Simulation results indicate that this novel design surpasses the previous fixed-width Booth multiplier in the precision of the product. An average error reduction of 65-84% compared with a direct-truncation fixed-width multiplier is achieved by adding only a few logic gates.},
keywords={},
doi={10.1093/ietfec/e90-a.6.1180},
ISSN={1745-1337},
month={June},}
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TY - JOUR
TI - Adaptive Low-Error Fixed-Width Booth Multipliers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1180
EP - 1187
AU - Min-An SONG
AU - Lan-Da VAN
AU - Sy-Yen KUO
PY - 2007
DO - 10.1093/ietfec/e90-a.6.1180
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2007
AB - In this paper, we propose two 2's-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best error-compensation bias in designing a multiplier suitable for VLSI implementation. Last but not least, we show the superior capability of our designs by inscribing it in a speech signal processor. Simulation results indicate that this novel design surpasses the previous fixed-width Booth multiplier in the precision of the product. An average error reduction of 65-84% compared with a direct-truncation fixed-width multiplier is achieved by adding only a few logic gates.
ER -
English
