IEICE TRANSACTIONS on Fundamentals
A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework
Summary :
Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. However, if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period. In experiments, the proposed method reduces the number of registers in the practical time in most circuits.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.10 pp.3030-3037
- Publication Date
- 2008/10/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e91-a.10.3030
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Yukihide KOHIRA, Atsushi TAKAHASHI, "A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 10, pp. 3030-3037, October 2008, doi: 10.1093/ietfec/e91-a.10.3030.
Abstract: Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. However, if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period. In experiments, the proposed method reduces the number of registers in the practical time in most circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.10.3030/_p
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@ARTICLE{e91-a_10_3030,
author={Yukihide KOHIRA, Atsushi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework},
year={2008},
volume={E91-A},
number={10},
pages={3030-3037},
abstract={Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. However, if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period. In experiments, the proposed method reduces the number of registers in the practical time in most circuits.},
keywords={},
doi={10.1093/ietfec/e91-a.10.3030},
ISSN={1745-1337},
month={October},}
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TY - JOUR
TI - A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3030
EP - 3037
AU - Yukihide KOHIRA
AU - Atsushi TAKAHASHI
PY - 2008
DO - 10.1093/ietfec/e91-a.10.3030
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2008
AB - Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. However, if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period. In experiments, the proposed method reduces the number of registers in the practical time in most circuits.
ER -
English
