IEICE TRANSACTIONS on Fundamentals
Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
Summary :
Leakage power consumption of logic elements has become a serious problem, especially in the sub-100-nanometer process. In this paper, a novel power gating approach by using the controlling value of logic elements is proposed. In the proposed method, sleep signals of the power-gated blocks are extracted completely from the original circuits without any extra logic element. A basic algorithm and a probability-based heuristic algorithm have been developed to implement the basic idea. The steady maximum delay constraint has also been introduced to handle the delay issues. Experiments on the ISCAS'85 benchmarks show that averagely 15-36% of logic elements could be power gated at a time for random input patterns, and 3-31% of elements could be stopped under the steady maximum delay constraints. We also show a power optimization method for AND/OR tree circuits, in which more than 80% of gates can be power-gated.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.12 pp.3531-3538
- Publication Date
- 2008/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e91-a.12.3531
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis, Test and Verification
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Lei CHEN, Takashi HORIYAMA, Yuichi NAKAMURA, Shinji KIMURA, "Fine-Grained Power Gating Based on the Controlling Value of Logic Elements" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 12, pp. 3531-3538, December 2008, doi: 10.1093/ietfec/e91-a.12.3531.
Abstract: Leakage power consumption of logic elements has become a serious problem, especially in the sub-100-nanometer process. In this paper, a novel power gating approach by using the controlling value of logic elements is proposed. In the proposed method, sleep signals of the power-gated blocks are extracted completely from the original circuits without any extra logic element. A basic algorithm and a probability-based heuristic algorithm have been developed to implement the basic idea. The steady maximum delay constraint has also been introduced to handle the delay issues. Experiments on the ISCAS'85 benchmarks show that averagely 15-36% of logic elements could be power gated at a time for random input patterns, and 3-31% of elements could be stopped under the steady maximum delay constraints. We also show a power optimization method for AND/OR tree circuits, in which more than 80% of gates can be power-gated.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3531/_p
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@ARTICLE{e91-a_12_3531,
author={Lei CHEN, Takashi HORIYAMA, Yuichi NAKAMURA, Shinji KIMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Fine-Grained Power Gating Based on the Controlling Value of Logic Elements},
year={2008},
volume={E91-A},
number={12},
pages={3531-3538},
abstract={Leakage power consumption of logic elements has become a serious problem, especially in the sub-100-nanometer process. In this paper, a novel power gating approach by using the controlling value of logic elements is proposed. In the proposed method, sleep signals of the power-gated blocks are extracted completely from the original circuits without any extra logic element. A basic algorithm and a probability-based heuristic algorithm have been developed to implement the basic idea. The steady maximum delay constraint has also been introduced to handle the delay issues. Experiments on the ISCAS'85 benchmarks show that averagely 15-36% of logic elements could be power gated at a time for random input patterns, and 3-31% of elements could be stopped under the steady maximum delay constraints. We also show a power optimization method for AND/OR tree circuits, in which more than 80% of gates can be power-gated.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3531},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3531
EP - 3538
AU - Lei CHEN
AU - Takashi HORIYAMA
AU - Yuichi NAKAMURA
AU - Shinji KIMURA
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3531
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - Leakage power consumption of logic elements has become a serious problem, especially in the sub-100-nanometer process. In this paper, a novel power gating approach by using the controlling value of logic elements is proposed. In the proposed method, sleep signals of the power-gated blocks are extracted completely from the original circuits without any extra logic element. A basic algorithm and a probability-based heuristic algorithm have been developed to implement the basic idea. The steady maximum delay constraint has also been introduced to handle the delay issues. Experiments on the ISCAS'85 benchmarks show that averagely 15-36% of logic elements could be power gated at a time for random input patterns, and 3-31% of elements could be stopped under the steady maximum delay constraints. We also show a power optimization method for AND/OR tree circuits, in which more than 80% of gates can be power-gated.
ER -
English
