Advanced Assertion-Based Design for Mixed-Signal Verification
Summary :
Functional and formal verification are important methodologies for complex mixed-signal design validation. However the industry is still verifying such systems by pure simulation. This process lacks on error localization and formal verifications methods. This is the existing verification gap between the analog and digital blocks within a mixed-signal system. Our approach improves the verification process by creating temporal properties named mixed-signal assertions which are described by a combination of digital assertions and analog properties. The proposed method is a new assertion-based verification flow for designing mixed-signal circuits. The effectiveness of the approach is demonstrated on a Σ/Δ-converter.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.12 pp.3548-3555
- Publication Date
- 2008/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e91-a.12.3548
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis, Test and Verification
Authors
Alexander JESSER
Stefan LAEMMERMANN
Alexander PACHOLIK
Roland WEISS
Juergen RUF
Lars HEDRICH
Wolfgang FENGLER
Thomas KROPF
Wolfgang ROSENSTIEL
Keyword
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Alexander JESSER, Stefan LAEMMERMANN, Alexander PACHOLIK, Roland WEISS, Juergen RUF, Lars HEDRICH, Wolfgang FENGLER, Thomas KROPF, Wolfgang ROSENSTIEL, "Advanced Assertion-Based Design for Mixed-Signal Verification" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 12, pp. 3548-3555, December 2008, doi: 10.1093/ietfec/e91-a.12.3548.
Abstract: Functional and formal verification are important methodologies for complex mixed-signal design validation. However the industry is still verifying such systems by pure simulation. This process lacks on error localization and formal verifications methods. This is the existing verification gap between the analog and digital blocks within a mixed-signal system. Our approach improves the verification process by creating temporal properties named mixed-signal assertions which are described by a combination of digital assertions and analog properties. The proposed method is a new assertion-based verification flow for designing mixed-signal circuits. The effectiveness of the approach is demonstrated on a Σ/Δ-converter.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3548/_p
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@ARTICLE{e91-a_12_3548,
author={Alexander JESSER, Stefan LAEMMERMANN, Alexander PACHOLIK, Roland WEISS, Juergen RUF, Lars HEDRICH, Wolfgang FENGLER, Thomas KROPF, Wolfgang ROSENSTIEL, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Advanced Assertion-Based Design for Mixed-Signal Verification},
year={2008},
volume={E91-A},
number={12},
pages={3548-3555},
abstract={Functional and formal verification are important methodologies for complex mixed-signal design validation. However the industry is still verifying such systems by pure simulation. This process lacks on error localization and formal verifications methods. This is the existing verification gap between the analog and digital blocks within a mixed-signal system. Our approach improves the verification process by creating temporal properties named mixed-signal assertions which are described by a combination of digital assertions and analog properties. The proposed method is a new assertion-based verification flow for designing mixed-signal circuits. The effectiveness of the approach is demonstrated on a Σ/Δ-converter.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3548},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Advanced Assertion-Based Design for Mixed-Signal Verification
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3548
EP - 3555
AU - Alexander JESSER
AU - Stefan LAEMMERMANN
AU - Alexander PACHOLIK
AU - Roland WEISS
AU - Juergen RUF
AU - Lars HEDRICH
AU - Wolfgang FENGLER
AU - Thomas KROPF
AU - Wolfgang ROSENSTIEL
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3548
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - Functional and formal verification are important methodologies for complex mixed-signal design validation. However the industry is still verifying such systems by pure simulation. This process lacks on error localization and formal verifications methods. This is the existing verification gap between the analog and digital blocks within a mixed-signal system. Our approach improves the verification process by creating temporal properties named mixed-signal assertions which are described by a combination of digital assertions and analog properties. The proposed method is a new assertion-based verification flow for designing mixed-signal circuits. The effectiveness of the approach is demonstrated on a Σ/Δ-converter.
ER -
English
