IEICE TRANSACTIONS on Fundamentals
A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits
Summary :
An algorithm for clock scheduling of concurrent-flow clocking rapid single-flux-quantum (RSFQ) digital circuits is proposed. RSFQ circuit technology is an emerging technology of digital circuits. In concurrent-flow clocking RSFQ digital circuits, all logic gates are driven by clock pulses. Appropriate clock scheduling makes clock frequency of the circuits higher. Given a clock period, the proposed algorithm determines the arrival time of clock pulses and the delay that should be inserted. Experimental results show that inserted delay elements by the proposed algorithm are 59.0% fewer and the height of clock trees are 40.4% shorter on average than those by a straightforward algorithm. The proposed algorithm can also be used to minimize the clock period, thus obtaining 19.0% shorter clock periods on average.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.12 pp.3772-3782
- Publication Date
- 2008/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e91-a.12.3772
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Keyword
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Koji OBATA, Kazuyoshi TAKAGI, Naofumi TAKAGI, "A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 12, pp. 3772-3782, December 2008, doi: 10.1093/ietfec/e91-a.12.3772.
Abstract: An algorithm for clock scheduling of concurrent-flow clocking rapid single-flux-quantum (RSFQ) digital circuits is proposed. RSFQ circuit technology is an emerging technology of digital circuits. In concurrent-flow clocking RSFQ digital circuits, all logic gates are driven by clock pulses. Appropriate clock scheduling makes clock frequency of the circuits higher. Given a clock period, the proposed algorithm determines the arrival time of clock pulses and the delay that should be inserted. Experimental results show that inserted delay elements by the proposed algorithm are 59.0% fewer and the height of clock trees are 40.4% shorter on average than those by a straightforward algorithm. The proposed algorithm can also be used to minimize the clock period, thus obtaining 19.0% shorter clock periods on average.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3772/_p
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@ARTICLE{e91-a_12_3772,
author={Koji OBATA, Kazuyoshi TAKAGI, Naofumi TAKAGI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits},
year={2008},
volume={E91-A},
number={12},
pages={3772-3782},
abstract={An algorithm for clock scheduling of concurrent-flow clocking rapid single-flux-quantum (RSFQ) digital circuits is proposed. RSFQ circuit technology is an emerging technology of digital circuits. In concurrent-flow clocking RSFQ digital circuits, all logic gates are driven by clock pulses. Appropriate clock scheduling makes clock frequency of the circuits higher. Given a clock period, the proposed algorithm determines the arrival time of clock pulses and the delay that should be inserted. Experimental results show that inserted delay elements by the proposed algorithm are 59.0% fewer and the height of clock trees are 40.4% shorter on average than those by a straightforward algorithm. The proposed algorithm can also be used to minimize the clock period, thus obtaining 19.0% shorter clock periods on average.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3772},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3772
EP - 3782
AU - Koji OBATA
AU - Kazuyoshi TAKAGI
AU - Naofumi TAKAGI
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3772
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - An algorithm for clock scheduling of concurrent-flow clocking rapid single-flux-quantum (RSFQ) digital circuits is proposed. RSFQ circuit technology is an emerging technology of digital circuits. In concurrent-flow clocking RSFQ digital circuits, all logic gates are driven by clock pulses. Appropriate clock scheduling makes clock frequency of the circuits higher. Given a clock period, the proposed algorithm determines the arrival time of clock pulses and the delay that should be inserted. Experimental results show that inserted delay elements by the proposed algorithm are 59.0% fewer and the height of clock trees are 40.4% shorter on average than those by a straightforward algorithm. The proposed algorithm can also be used to minimize the clock period, thus obtaining 19.0% shorter clock periods on average.
ER -
English
