IEICE TRANSACTIONS on Fundamentals
An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches
Summary :
This paper deals with redundant 3D mesh processor arrays using 1.5-track switches, considering track and switch faults together with processor faults. Four variants are defined based on the distributions of spare PEs, and arrays of three variants have the same PE redundancies among them, but the fabrication-time costs are different. We investigate in detail how the reliability of a total system changes according to the reliabilities of tracks and switches as well as PEs, and show the concrete values of Mt and Ms, when the reliability of array are almost the same even if its variant is changed, and when it is not so, respectively, where Mt and Ms are the ratio of the hardware complexities of a PE and a track, and that of a PE and a contact point of a switch, respectively. Other results which are effective basis for the design of fault-tolerant 3D PE arrays using 1.5-TSs are given.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.2 pp.623-632
- Publication Date
- 2008/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e91-a.2.623
- Type of Manuscript
- PAPER
- Category
- Reliability, Maintainability and Safety Analysis
Authors
Keyword
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Tadayoshi HORITA, Yuuji KATOU, Itsuo TAKANAMI, "An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 2, pp. 623-632, February 2008, doi: 10.1093/ietfec/e91-a.2.623.
Abstract: This paper deals with redundant 3D mesh processor arrays using 1.5-track switches, considering track and switch faults together with processor faults. Four variants are defined based on the distributions of spare PEs, and arrays of three variants have the same PE redundancies among them, but the fabrication-time costs are different. We investigate in detail how the reliability of a total system changes according to the reliabilities of tracks and switches as well as PEs, and show the concrete values of Mt and Ms, when the reliability of array are almost the same even if its variant is changed, and when it is not so, respectively, where Mt and Ms are the ratio of the hardware complexities of a PE and a track, and that of a PE and a contact point of a switch, respectively. Other results which are effective basis for the design of fault-tolerant 3D PE arrays using 1.5-TSs are given.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.2.623/_p
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@ARTICLE{e91-a_2_623,
author={Tadayoshi HORITA, Yuuji KATOU, Itsuo TAKANAMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches},
year={2008},
volume={E91-A},
number={2},
pages={623-632},
abstract={This paper deals with redundant 3D mesh processor arrays using 1.5-track switches, considering track and switch faults together with processor faults. Four variants are defined based on the distributions of spare PEs, and arrays of three variants have the same PE redundancies among them, but the fabrication-time costs are different. We investigate in detail how the reliability of a total system changes according to the reliabilities of tracks and switches as well as PEs, and show the concrete values of Mt and Ms, when the reliability of array are almost the same even if its variant is changed, and when it is not so, respectively, where Mt and Ms are the ratio of the hardware complexities of a PE and a track, and that of a PE and a contact point of a switch, respectively. Other results which are effective basis for the design of fault-tolerant 3D PE arrays using 1.5-TSs are given.},
keywords={},
doi={10.1093/ietfec/e91-a.2.623},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 623
EP - 632
AU - Tadayoshi HORITA
AU - Yuuji KATOU
AU - Itsuo TAKANAMI
PY - 2008
DO - 10.1093/ietfec/e91-a.2.623
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2008
AB - This paper deals with redundant 3D mesh processor arrays using 1.5-track switches, considering track and switch faults together with processor faults. Four variants are defined based on the distributions of spare PEs, and arrays of three variants have the same PE redundancies among them, but the fabrication-time costs are different. We investigate in detail how the reliability of a total system changes according to the reliabilities of tracks and switches as well as PEs, and show the concrete values of Mt and Ms, when the reliability of array are almost the same even if its variant is changed, and when it is not so, respectively, where Mt and Ms are the ratio of the hardware complexities of a PE and a track, and that of a PE and a contact point of a switch, respectively. Other results which are effective basis for the design of fault-tolerant 3D PE arrays using 1.5-TSs are given.
ER -
English
