Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player

Sumek WISAYATAKSIN; Dongju LI; Tsuyoshi ISSHIKI; Hiroaki KUNIEDA

doi:10.1093/ietfec/e91-a.4.1197

Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player

Sumek WISAYATAKSIN, Dongju LI, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA

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We propose a low cost and stand-alone platform-based SoC for H.264/AVC decoder, whose target is practical mobile applications such as a handheld video player. Both low cost and stand-alone solutions are particularly emphasized. The SoC, consisting of RISC core and decoder core, has advantages in terms of flexibility, testability and various I/O interfaces. For decoder core design, the proposed H.264/AVC coprocessor in the SoC employs a new block pipelining scheme instead of a conventional macroblock or a hybrid one, which greatly contribute to reducing drastically the size of the core and its pipelining buffer. In addition, the decoder schedule is optimized to block level which is easy to be programmed. Actually, the core size is reduced to 138 KGate with 3.5 kbyte memory. In our practical development, a single external SDRAM is sufficient for both reference frame buffer and display buffer. Various peripheral interfaces such as a compact flash, a digital broadcast receiver and a LCD driver are also provided on a chip.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.4 pp.1197-1205

Publication Date: 2008/04/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e91-a.4.1197

Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

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Sumek WISAYATAKSIN, Dongju LI, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA, "Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player" in IEICE TRANSACTIONS on Fundamentals, vol. E91-A, no. 4, pp. 1197-1205, April 2008, doi: 10.1093/ietfec/e91-a.4.1197.
Abstract: We propose a low cost and stand-alone platform-based SoC for H.264/AVC decoder, whose target is practical mobile applications such as a handheld video player. Both low cost and stand-alone solutions are particularly emphasized. The SoC, consisting of RISC core and decoder core, has advantages in terms of flexibility, testability and various I/O interfaces. For decoder core design, the proposed H.264/AVC coprocessor in the SoC employs a new block pipelining scheme instead of a conventional macroblock or a hybrid one, which greatly contribute to reducing drastically the size of the core and its pipelining buffer. In addition, the decoder schedule is optimized to block level which is easy to be programmed. Actually, the core size is reduced to 138 KGate with 3.5 kbyte memory. In our practical development, a single external SDRAM is sufficient for both reference frame buffer and display buffer. Various peripheral interfaces such as a compact flash, a digital broadcast receiver and a LCD driver are also provided on a chip.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.4.1197/_p

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@ARTICLE{e91-a_4_1197,
author={Sumek WISAYATAKSIN, Dongju LI, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player},
year={2008},
volume={E91-A},
number={4},
pages={1197-1205},
abstract={We propose a low cost and stand-alone platform-based SoC for H.264/AVC decoder, whose target is practical mobile applications such as a handheld video player. Both low cost and stand-alone solutions are particularly emphasized. The SoC, consisting of RISC core and decoder core, has advantages in terms of flexibility, testability and various I/O interfaces. For decoder core design, the proposed H.264/AVC coprocessor in the SoC employs a new block pipelining scheme instead of a conventional macroblock or a hybrid one, which greatly contribute to reducing drastically the size of the core and its pipelining buffer. In addition, the decoder schedule is optimized to block level which is easy to be programmed. Actually, the core size is reduced to 138 KGate with 3.5 kbyte memory. In our practical development, a single external SDRAM is sufficient for both reference frame buffer and display buffer. Various peripheral interfaces such as a compact flash, a digital broadcast receiver and a LCD driver are also provided on a chip.},
keywords={},
doi={10.1093/ietfec/e91-a.4.1197},
ISSN={1745-1337},
month={April},}

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TY - JOUR
TI - Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1197
EP - 1205
AU - Sumek WISAYATAKSIN
AU - Dongju LI
AU - Tsuyoshi ISSHIKI
AU - Hiroaki KUNIEDA
PY - 2008
DO - 10.1093/ietfec/e91-a.4.1197
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2008
AB - We propose a low cost and stand-alone platform-based SoC for H.264/AVC decoder, whose target is practical mobile applications such as a handheld video player. Both low cost and stand-alone solutions are particularly emphasized. The SoC, consisting of RISC core and decoder core, has advantages in terms of flexibility, testability and various I/O interfaces. For decoder core design, the proposed H.264/AVC coprocessor in the SoC employs a new block pipelining scheme instead of a conventional macroblock or a hybrid one, which greatly contribute to reducing drastically the size of the core and its pipelining buffer. In addition, the decoder schedule is optimized to block level which is easy to be programmed. Actually, the core size is reduced to 138 KGate with 3.5 kbyte memory. In our practical development, a single external SDRAM is sufficient for both reference frame buffer and display buffer. Various peripheral interfaces such as a compact flash, a digital broadcast receiver and a LCD driver are also provided on a chip.
ER -