A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission

Masayuki MIYAMA; Yuusuke INOIE; Takafumi KASUGA; Ryouichi INADA; Masashi NAKAO; Yoshio MATSUDA

doi:10.1093/ietfec/e91-a.8.2025

A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission

Masayuki MIYAMA, Yuusuke INOIE, Takafumi KASUGA, Ryouichi INADA, Masashi NAKAO, Yoshio MATSUDA

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This paper describes a 158 MS/s JPEG 2000 codec with an embedded block coder (EBC) based on bit-plane and pass-parallel architecture. The EBC contains bit-plane coders (BPCs) corresponding to each bit-plane in a code-block. The upper and the lower bit-plane coding overlap in time with a 1-stripe and 1-column gap. The bit-modeling passes in the bit-plane coding also overlap in time with the same gap. These methods increase throughput by 30 times in comparison with the conventional. In addition, the methods support not only vertically causal mode, but also regular mode, which enhances the image quality. Furthermore, speculative decoding is adopted to increase throughput. This codec LSI was designed using 0.18 µm process. The core area is 4.74.7 mm² and the frequency is 160 MHz. A system including the codec enables image transmission of PC desktop with 8 ms delay.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.8 pp.2025-2034

Publication Date: 2008/08/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e91-a.8.2025

Type of Manuscript: Special Section PAPER (Special Section on Signal Processing)

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Masayuki MIYAMA, Yuusuke INOIE, Takafumi KASUGA, Ryouichi INADA, Masashi NAKAO, Yoshio MATSUDA, "A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission" in IEICE TRANSACTIONS on Fundamentals, vol. E91-A, no. 8, pp. 2025-2034, August 2008, doi: 10.1093/ietfec/e91-a.8.2025.
Abstract: This paper describes a 158 MS/s JPEG 2000 codec with an embedded block coder (EBC) based on bit-plane and pass-parallel architecture. The EBC contains bit-plane coders (BPCs) corresponding to each bit-plane in a code-block. The upper and the lower bit-plane coding overlap in time with a 1-stripe and 1-column gap. The bit-modeling passes in the bit-plane coding also overlap in time with the same gap. These methods increase throughput by 30 times in comparison with the conventional. In addition, the methods support not only vertically causal mode, but also regular mode, which enhances the image quality. Furthermore, speculative decoding is adopted to increase throughput. This codec LSI was designed using 0.18 µm process. The core area is 4.74.7 mm² and the frequency is 160 MHz. A system including the codec enables image transmission of PC desktop with 8 ms delay.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.8.2025/_p

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@ARTICLE{e91-a_8_2025,
author={Masayuki MIYAMA, Yuusuke INOIE, Takafumi KASUGA, Ryouichi INADA, Masashi NAKAO, Yoshio MATSUDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission},
year={2008},
volume={E91-A},
number={8},
pages={2025-2034},
abstract={This paper describes a 158 MS/s JPEG 2000 codec with an embedded block coder (EBC) based on bit-plane and pass-parallel architecture. The EBC contains bit-plane coders (BPCs) corresponding to each bit-plane in a code-block. The upper and the lower bit-plane coding overlap in time with a 1-stripe and 1-column gap. The bit-modeling passes in the bit-plane coding also overlap in time with the same gap. These methods increase throughput by 30 times in comparison with the conventional. In addition, the methods support not only vertically causal mode, but also regular mode, which enhances the image quality. Furthermore, speculative decoding is adopted to increase throughput. This codec LSI was designed using 0.18 µm process. The core area is 4.74.7 mm² and the frequency is 160 MHz. A system including the codec enables image transmission of PC desktop with 8 ms delay.},
keywords={},
doi={10.1093/ietfec/e91-a.8.2025},
ISSN={1745-1337},
month={August},}

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TY - JOUR
TI - A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2025
EP - 2034
AU - Masayuki MIYAMA
AU - Yuusuke INOIE
AU - Takafumi KASUGA
AU - Ryouichi INADA
AU - Masashi NAKAO
AU - Yoshio MATSUDA
PY - 2008
DO - 10.1093/ietfec/e91-a.8.2025
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2008
AB - This paper describes a 158 MS/s JPEG 2000 codec with an embedded block coder (EBC) based on bit-plane and pass-parallel architecture. The EBC contains bit-plane coders (BPCs) corresponding to each bit-plane in a code-block. The upper and the lower bit-plane coding overlap in time with a 1-stripe and 1-column gap. The bit-modeling passes in the bit-plane coding also overlap in time with the same gap. These methods increase throughput by 30 times in comparison with the conventional. In addition, the methods support not only vertically causal mode, but also regular mode, which enhances the image quality. Furthermore, speculative decoding is adopted to increase throughput. This codec LSI was designed using 0.18 µm process. The core area is 4.74.7 mm² and the frequency is 160 MHz. A system including the codec enables image transmission of PC desktop with 8 ms delay.
ER -