IEICE TRANSACTIONS on Fundamentals
Post-Silicon Clock-Timing Tuning Based on Statistical Estimation
Summary :
In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs' clock timing and presuming the rest of FFs' clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.9 pp.2322-2327
- Publication Date
- 2008/09/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e91-a.9.2322
- Type of Manuscript
- Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
- Category
Authors
Keyword
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Yuko HASHIZUME, Yasuhiro TAKASHIMA, Yuichi NAKAMURA, "Post-Silicon Clock-Timing Tuning Based on Statistical Estimation" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 9, pp. 2322-2327, September 2008, doi: 10.1093/ietfec/e91-a.9.2322.
Abstract: In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs' clock timing and presuming the rest of FFs' clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.9.2322/_p
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@ARTICLE{e91-a_9_2322,
author={Yuko HASHIZUME, Yasuhiro TAKASHIMA, Yuichi NAKAMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Post-Silicon Clock-Timing Tuning Based on Statistical Estimation},
year={2008},
volume={E91-A},
number={9},
pages={2322-2327},
abstract={In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs' clock timing and presuming the rest of FFs' clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.},
keywords={},
doi={10.1093/ietfec/e91-a.9.2322},
ISSN={1745-1337},
month={September},}
Copy
TY - JOUR
TI - Post-Silicon Clock-Timing Tuning Based on Statistical Estimation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2322
EP - 2327
AU - Yuko HASHIZUME
AU - Yasuhiro TAKASHIMA
AU - Yuichi NAKAMURA
PY - 2008
DO - 10.1093/ietfec/e91-a.9.2322
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2008
AB - In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs' clock timing and presuming the rest of FFs' clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.
ER -
English
