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Post-Silicon Clock-Timing Tuning Based on Statistical Estimation

Yuko HASHIZUME, Yasuhiro TAKASHIMA, Yuichi NAKAMURA

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Summary :

In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs' clock timing and presuming the rest of FFs' clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.9 pp.2322-2327
Publication Date
2008/09/01
Publicized
Online ISSN
1745-1337
DOI
10.1093/ietfec/e91-a.9.2322
Type of Manuscript
Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
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