IEICE TRANSACTIONS on Fundamentals
A CMOS Cell Compiler for a Bit-Mapping CAD System
Summary :
In this paper, the CMOS Cell Compiler (CCC) which was developed on our bit-mapping CAD is introduced. The CCC generates the physical layout for a logic cell from a functional description expressed by a set of Boolean equations. A CMOS digital LSI having up to 104 transistors can be designed on this bit-mapping CAD by placing a physical layout of cells generated on the bit-map editor and by giving interconnections manually among the cells. The physical layout obeys λ-base design rule on a bit-map grid plane and can support single-and double-metal CMOS process. An aspect ratio and a position of input and output terminals in a rectangle cell are depending on functional description of Boolean equations.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E74-A No.9 pp.2603-2611
- Publication Date
- 1991/09/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Computer Aided Design (CAD)
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Cong-Kha PHAM, Katsufusa SHONO, "A CMOS Cell Compiler for a Bit-Mapping CAD System" in IEICE TRANSACTIONS on Fundamentals,
vol. E74-A, no. 9, pp. 2603-2611, September 1991, doi: .
Abstract: In this paper, the CMOS Cell Compiler (CCC) which was developed on our bit-mapping CAD is introduced. The CCC generates the physical layout for a logic cell from a functional description expressed by a set of Boolean equations. A CMOS digital LSI having up to 104 transistors can be designed on this bit-mapping CAD by placing a physical layout of cells generated on the bit-map editor and by giving interconnections manually among the cells. The physical layout obeys λ-base design rule on a bit-map grid plane and can support single-and double-metal CMOS process. An aspect ratio and a position of input and output terminals in a rectangle cell are depending on functional description of Boolean equations.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e74-a_9_2603/_p
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@ARTICLE{e74-a_9_2603,
author={Cong-Kha PHAM, Katsufusa SHONO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A CMOS Cell Compiler for a Bit-Mapping CAD System},
year={1991},
volume={E74-A},
number={9},
pages={2603-2611},
abstract={In this paper, the CMOS Cell Compiler (CCC) which was developed on our bit-mapping CAD is introduced. The CCC generates the physical layout for a logic cell from a functional description expressed by a set of Boolean equations. A CMOS digital LSI having up to 104 transistors can be designed on this bit-mapping CAD by placing a physical layout of cells generated on the bit-map editor and by giving interconnections manually among the cells. The physical layout obeys λ-base design rule on a bit-map grid plane and can support single-and double-metal CMOS process. An aspect ratio and a position of input and output terminals in a rectangle cell are depending on functional description of Boolean equations.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - A CMOS Cell Compiler for a Bit-Mapping CAD System
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2603
EP - 2611
AU - Cong-Kha PHAM
AU - Katsufusa SHONO
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E74-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 1991
AB - In this paper, the CMOS Cell Compiler (CCC) which was developed on our bit-mapping CAD is introduced. The CCC generates the physical layout for a logic cell from a functional description expressed by a set of Boolean equations. A CMOS digital LSI having up to 104 transistors can be designed on this bit-mapping CAD by placing a physical layout of cells generated on the bit-map editor and by giving interconnections manually among the cells. The physical layout obeys λ-base design rule on a bit-map grid plane and can support single-and double-metal CMOS process. An aspect ratio and a position of input and output terminals in a rectangle cell are depending on functional description of Boolean equations.
ER -
English
