IEICE TRANSACTIONS on Fundamentals
An Optimum Placement of Capacitors in the Layout of Switched Capacitor Networks
Summary :
An optimum placement of capacitors in the layout of Switched Capacitor networks is presented in this paper. The performance of integrated circuits is generally degraded by perturbations of physical parameters of each device and parasitic strays. The optimality imposed in this paper is the minimum degradation of a transfer function with respect to the distribution of capacitance values. A capacitance value per unit area fabricated on a LSI chip is assumed to be perturbed linearly with its x and y coordinates. The capacitor placement is determined so that the effects of such perturbation of capacitances to the overall transfer-characteristics are canceled. As the result, input-output transfer function will stay nominal under the linear perturbation model with arbitrary gradients.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E75-A No.2 pp.215-223
- Publication Date
- 1992/02/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Analog Circuits and Signal Processing
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Mineo KANEKO, Kimihiko KAZUI, Hiroaki KUNIEDA, "An Optimum Placement of Capacitors in the Layout of Switched Capacitor Networks" in IEICE TRANSACTIONS on Fundamentals,
vol. E75-A, no. 2, pp. 215-223, February 1992, doi: .
Abstract: An optimum placement of capacitors in the layout of Switched Capacitor networks is presented in this paper. The performance of integrated circuits is generally degraded by perturbations of physical parameters of each device and parasitic strays. The optimality imposed in this paper is the minimum degradation of a transfer function with respect to the distribution of capacitance values. A capacitance value per unit area fabricated on a LSI chip is assumed to be perturbed linearly with its x and y coordinates. The capacitor placement is determined so that the effects of such perturbation of capacitances to the overall transfer-characteristics are canceled. As the result, input-output transfer function will stay nominal under the linear perturbation model with arbitrary gradients.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e75-a_2_215/_p
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@ARTICLE{e75-a_2_215,
author={Mineo KANEKO, Kimihiko KAZUI, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Optimum Placement of Capacitors in the Layout of Switched Capacitor Networks},
year={1992},
volume={E75-A},
number={2},
pages={215-223},
abstract={An optimum placement of capacitors in the layout of Switched Capacitor networks is presented in this paper. The performance of integrated circuits is generally degraded by perturbations of physical parameters of each device and parasitic strays. The optimality imposed in this paper is the minimum degradation of a transfer function with respect to the distribution of capacitance values. A capacitance value per unit area fabricated on a LSI chip is assumed to be perturbed linearly with its x and y coordinates. The capacitor placement is determined so that the effects of such perturbation of capacitances to the overall transfer-characteristics are canceled. As the result, input-output transfer function will stay nominal under the linear perturbation model with arbitrary gradients.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - An Optimum Placement of Capacitors in the Layout of Switched Capacitor Networks
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 215
EP - 223
AU - Mineo KANEKO
AU - Kimihiko KAZUI
AU - Hiroaki KUNIEDA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E75-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1992
AB - An optimum placement of capacitors in the layout of Switched Capacitor networks is presented in this paper. The performance of integrated circuits is generally degraded by perturbations of physical parameters of each device and parasitic strays. The optimality imposed in this paper is the minimum degradation of a transfer function with respect to the distribution of capacitance values. A capacitance value per unit area fabricated on a LSI chip is assumed to be perturbed linearly with its x and y coordinates. The capacitor placement is determined so that the effects of such perturbation of capacitances to the overall transfer-characteristics are canceled. As the result, input-output transfer function will stay nominal under the linear perturbation model with arbitrary gradients.
ER -
English
